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A Low Overhead Fault Reporting Scheme for Resilient 3D Network-on-Chip Applications

Michael Opoku Agyeman. Published in Networks.

Communications on Applied Electronics
Year of Publication: 2015
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Michael Opoku Agyeman
10.5120/cae2015651744

Michael Opoku Agyeman. Article: A Low Overhead Fault Reporting Scheme for Resilient 3D Network-on-Chip Applications. Communications on Applied Electronics 2(4):43-48, July 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Michael Opoku Agyeman},
	title = {Article: A Low Overhead Fault Reporting Scheme for Resilient 3D Network-on-Chip Applications},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {2},
	number = {4},
	pages = {43-48},
	month = {July},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

Recently three-dimensional Networks-on-Chips (3D NoCs) ranging from regular to highly irregular topologies have been realized as efforts to improve the performance of applications in both general purpose and application-specific multi-core domain. However, faults can cause high contentions in NoCs. As a solution, adaptive routing algorithms are used. On the other hand, these algorithms have high area and timing overheads due to extra logic required for adaptively. We present a novel fault reporting scheme as well as a fault-tolerant routing algorithm for emerging 3D NoCs. The proposed algorithm analyses the condition of the NoC resources and distance of the destination nodes to reroute packets. The algorithm has been evaluated by synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm has significant reduction in packet delays (over 45%) compared to other algorithms.

References

  1. M.A. Al Faruque and J. Henkel. Minimizing virtual channel buffer for routers in on-chip communication architectures. In Design, Automation and Test in Europe (DATE), pages 1238 –1243, march 2008.
  2. L. Benini and G. De Micheli. Networks on chips: a new SoC paradigm. Computer, 35(1):70–78, 2002.
  3. Jun Chen, Du Xu, and Ling fu Xie. A fault-tolerant routing protocol in 2d torus based on positive-first and negativefirst turn models. In International Conference on Information Engineering and Computer Science (ICIECS), pages 1–5, 2009.
  4. Glass Christopher J and Lionel M. Ni. Fault-tolerant wormhole routing in meshes without virtual channels. IEEE Transactions on Parallel and Distributed Systems, 7(6):620–636, 1996.
  5. R. Dick. Embedded system synthesis benchmarks suite(e3s). http://ziyang.eecs.umich.edu/dickrp/e3s/. Accessed: 06/2010.
  6. F. Dubois, A. Sheibanyrad, F. Petrot, and M. Bahmani. Elevator-first: a deadlock-free distributed routing algorithm for vertically partially connected 3d-nocs. IEEE Transactions on Computers, PP(99):1, 2011.
  7. V. Dumitriu and G.N. Khan. Throughput-oriented noc topology generation and analysis for high performance socs. VLSI, 17(10):1433 –1446, 2009.
  8. Mar´ia Engracia G´omez, Jos´e Duato, Jose Flich, Pedro L´opez, Antonio Robles, Nils Agne Nordbotten, Olav Lysne, and Tor Skeie. An efficient fault-tolerant routing methodology for meshes and tori. Computer Architecture Letters, 3, 2004.
  9. Jingcao Hu and R. Marculescu. Dyad - smart routing for networks-on-chip. In Design Automation Conference(DAC), pages 260 – 263, 2004.
  10. Jingcao Hu and R. Marculescu. Energy- and performanceaware mapping for regular NoC architectures. Computer- Aided Design of Integrated Circuits and Systems, 24(4):551–562, 2005.
  11. G. De Micheli and L. Benini. Networks on Chips: Technology and Tools. Morgan Kaufmann, First Edition, 2006.
  12. Partha Pratim Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. on Computers, 54(8):1025–1040, 2005.
  13. Vasilis F. Pavlidis and Eby G. Friedman. Interconnect delay minimization through interlayer via placement. In in 3-D ICs,in Proc. Great Lakes Symposum on VLSI, pages 20–25, 2005.
  14. V. Puente, J.A. Gregorio, F. Vallejo, and R. Beivide. Immunet: a cheap and robust fault-tolerant packet routing mechanism. In Annual International Symposium on Computer Architecture, pages 198 – 209, 2004.
  15. S. Rodrigo, J. Flich, J. Duato, and M. Hummel. Efficient unicast and multicast support for cmps. In IEEE/ACM International Symposium on Microarchitecture (MICRO-41)., pages 364 –375, 2008.
  16. Claudia Rusu, Lorena Anghel, and Dimiter Avresky. Rilm: Reconfigurable inter-layer routing mechanism for 3d multilayer networks-on-chip. IEEE International On-Line Testing Symposium, 0:121–126, 2010.
  17. M. Valinataj and S. Mohammadi. A fault-aware, reconfigurable and adaptive routing algorithm for noc applications. In IEEE/IFIP VLSI System on Chip Conference (VLSISoC), pages 13 –18, sept. 2010.
  18. JieWu. A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans. on Computers, 52(9):1154 – 1169, 2003.
  19. Terry Tao Ye, Giovanni De Micheli, and Luca Benini. Analysis of power consumption on switch fabrics in network routers. In DAC, pages 524 – 529, 2002.
  20. Jipeng Zhou and Francis C.M. Lau. Multi-phase minimal fault-tolerant wormhole routing in meshes. Parallel Computing, 30(3):423 – 442.

Keywords

Networks-on-Chip, Fault-tolerant, Routing algorithms