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Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications

M. Rafat M., Mohamed H. El-Mahlawy, A.H. Zaki, M.S. Hamid. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2015
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: M. Rafat M., Mohamed H. El-Mahlawy, A.H. Zaki, M.S. Hamid

Rafat M M., Mohamed H El-Mahlawy, A H Zaki and M S Hamid. Article: Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications. Communications on Applied Electronics 2(8):25-37, September 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

	author = {M. Rafat M. and Mohamed H. El-Mahlawy and A.H. Zaki and M.S. Hamid},
	title = {Article: Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {2},
	number = {8},
	pages = {25-37},
	month = {September},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}


This paper targets the design of a high dynamic range low-power, low-noise pixel readout integrated circuit (ROIC) that handles the infrared (IR) detector’s output signal of the uncooled thermal IR camera. Throughout the paper, both the optics and the IR detector modules of the IR camera are modeled using the analogue hardware description language (AHDL) to enable extracting the proper input signal required for the ROIC design. A capacitive trans-impedance amplifier (CTIA) is selected for design as a column level ROIC. The core of the CTIA is designed for minimum power consumption by operation in the sub-threshold region. In addition, a design of correlated double sampling (CDS) technique is applied to the CTIA to minimize the noise and the offset levels. The presented CTIA design achieves a power consumption of 5.2μW and root mean square (RMS) output noise of 6.9μV. All the circuits were implemented in 0.13µm CMOS process technology. The design rule check (DRC), layout versus schematic (LVS), parasitic extraction (PE), Process-voltage-temperature (PVT) analysis and post-layout simulation are performed for all designed circuits. The post-layout simulation results illustrate enhancement of the power consumption and noise performance compared to other published ROIC designs. Finally, a new widening dynamic range (WDR) technique is applied to the CTIA with the CDS circuit designs to increase the dynamic range (DR).


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WDR, CTIA, ROIC, CDS, Thermal imaging