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FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation

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Noor Kareem Jumaa. Published in Parallel Computing.

FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation
Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Series: Volume 5 Number 1
Authors: Noor Kareem Jumaa
10.5120/cae2016652048
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Noor Kareem Jumaa. FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation. Communications on Applied Electronics 5(1):6-12, May 2016. BibTeX

@article{10.5120/cae2016652048,
	author = {Noor Kareem Jumaa},
	title = {FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation},
	journal = {Communications on Applied Electronics},
	issue_date = {May 2016},
	volume = {5},
	number = {1},
	month = {May},
	year = {2016},
	issn = {2394-4714},
	pages = {6-12},
	numpages = {7},
	url = {http://www.caeaccess.org/archives/volume5/number1/585-2016652048},
	doi = {10.5120/cae2016652048},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Systolic array computation can be done by the arrangement of multi processors in an array which enables the data to follows synchronously across the array and between neighbor processor which speeded up the computation comparing with single processor computation. A sinusoidal sequence is generated in a considerably shorter time by using a fully pipelined systolic array.

FPGA (Field Programmable Gate Array) is selected as a VLSI (Very Large Scale Integration) platform device since, FPGA can provide a certain computations at very high frequencies with systolic computing. The present work is concentrated on developing hardware model for systolic array implementation for sinusoidal sequence generator using VHDL (Very High Speed Integrated Circuits Hardware Description Language) as a platform. The design is implemented using simulator and synthesized on Cyclone III FPGA board.

References

  1. Bairu K. Saptalakar, Deepak Kale, Mahesh Rachannavar, and Pavankumar M. K., "Design and Implemetation of VLSI Systolic Array Multiplier for DSP Applications", International Journal of Scientific Engineering and Technology, Vol. 2, ISSN: 2277-1581, India, 2013. VLIS
  2. Himani, Harmanbir Singh Sidhu, "Design and Implementation Modified Both Algorithm and Systolic Multiplier Using FPGA", International Journal of Engineering Research & Technology (IJERT), Vol.2, ISSN: 2278-0181 ,2013.
  3. Rakesh Birle and Lalit Bandil, "Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication", International Journal of Engineering and Advanced Technology (IJEAT), Vol. 1, ISSN: 2249-8958, India, 2012. VLIS
  4. Nuha A.S. Alwan, "A Fully Pipelined Systolic Array for Sinusoidal sequence Generation", IEEE Transactions on Computers, Vol. 55, No. 5, 2006.

Keywords

Systolic Array, FPGA, VLSI, VHDL, Altera