Call for Paper

CAE solicits original research papers for the July 2021 Edition. Last date of manuscript submission is June 30, 2021.

Read More

Low Power High Speed Multiplier Design based on MTCMOS Technique

Amrita Oza, Poonam Kadam. Published in Power Electronics.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Amrita Oza, Poonam Kadam

Amrita Oza and Poonam Kadam. Low Power High Speed Multiplier Design based on MTCMOS Technique. Communications on Applied Electronics 5(7):18-21, July 2016. BibTeX

	author = {Amrita Oza and Poonam Kadam},
	title = {Low Power High Speed Multiplier Design based on MTCMOS Technique},
	journal = {Communications on Applied Electronics},
	issue_date = {July 2016},
	volume = {5},
	number = {7},
	month = {Jul},
	year = {2016},
	issn = {2394-4714},
	pages = {18-21},
	numpages = {4},
	url = {},
	doi = {10.5120/cae2016652318},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


The need for devices that consume minimum amount of power was a major driving force behind the development of CMOS technologies. Reduction of power consumption makes a device more reliable. As a result, CMOS devices are best known for low power consumption. Most research on the power consumption of circuits has been focused on the switching power and the power dissipated by the leakage current has been comparatively minor area. Today, every designer either analog circuit or a digital circuit designer is concerned about the amount of power consumption in the circuit at the end. Multi-threshold CMOS is becoming a trendy circuit design technique for low power, high performance application. The paper briefs the implementation of a novel CMOS 8 bit Vedic Multiplier using MTCMOS.


  1. Manish Kumar, Md. Anwar Hussain, Sajal K. Paul“An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage”, Scientific Research, Circuits and Systems, 2013, 4, 431-437.
  2. Kyung Ki Kim and Yong-Bin Kim, Nohpill Park, Minsu Choi, “Leakage Minimization Techniques for Nanoscale CMOS VLSI”, Computer-Aided Design for Emerging Technologies , 2007, IEEE Design & Test of Computers.
  3. Hesham A. Al-Twaijry, Michael J. Flynn,” Technology Scaling Effects on Multipliers”, IEEE Transactions on Computers, vol. 47, No. 11, pp.1201-1215, November 1998.
  4. N.Rajput, M.Sethi, P.Dobriyal, K.Sharma, G.Sharma, “A Novel, High Performance and Power Efficient Implementation of 8x8 Multiplier Unit using MT-CMOS Technique” , 978-1-4799-0192-0/13/ ©2013 IEEE
  5. J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.
  6. B.S. Deepaksubramanyan and Adrian Nu˜nez, “Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits”, Proceedings of the 13th NASA VLSI Symposium, Post Falls, IDAHO, USA, JUNE 5-6, 2007.
  7. James Kao, Anantha Chandrakasan, Dimitri Antoniadis, “Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology” DAC 97, Anaheim, California (c) 1997 ACM 0-89791-920-3/97/06
  8. Arushi Somani, Dheeraj Jain,et. al., “Compare Vedic Multipliers with Conventional Hierarchical array of multiplier”, International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 2, Issue 6.
  9. Jagannath Samanta, Mousam Halder, Bishnu Prasad De, “Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles” (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, Jan- 2013
  10. Manash Chanda, Sankalp Jain, Swapnadip De Chandan Kumar Sarkar, “Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application”, IEEE Transactions on VLSI System.
  11. Amita, Mrs. Nitin Sachdeva, “Design and Analysis of Carry Look Ahead Adder Using CMOS Technique”, (IOSR-JECE) p- ISSN: 2278-8735.Volume 9, Issue 2, Ver. VII (Mar - Apr. 2014), PP 92-9.


MTCMOS (Multi threshold CMOS), Sub-threshold leakage current, Vedic Mathematics, Urdhva Tiryagbhyam Sutra.