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Low Power High Speed Multiplier Design based on MTCMOS Technique

Amrita Oza, Poonam Kadam. Published in Power Electronics.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Amrita Oza, Poonam Kadam
10.5120/cae2016652318

Amrita Oza and Poonam Kadam. Low Power High Speed Multiplier Design based on MTCMOS Technique. Communications on Applied Electronics 5(7):18-21, July 2016. BibTeX

@article{10.5120/cae2016652318,
	author = {Amrita Oza and Poonam Kadam},
	title = {Low Power High Speed Multiplier Design based on MTCMOS Technique},
	journal = {Communications on Applied Electronics},
	issue_date = {July 2016},
	volume = {5},
	number = {7},
	month = {Jul},
	year = {2016},
	issn = {2394-4714},
	pages = {18-21},
	numpages = {4},
	url = {http://www.caeaccess.org/archives/volume5/number7/632-2016652318},
	doi = {10.5120/cae2016652318},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

The need for devices that consume minimum amount of power was a major driving force behind the development of CMOS technologies. Reduction of power consumption makes a device more reliable. As a result, CMOS devices are best known for low power consumption. Most research on the power consumption of circuits has been focused on the switching power and the power dissipated by the leakage current has been comparatively minor area. Today, every designer either analog circuit or a digital circuit designer is concerned about the amount of power consumption in the circuit at the end. Multi-threshold CMOS is becoming a trendy circuit design technique for low power, high performance application. The paper briefs the implementation of a novel CMOS 8 bit Vedic Multiplier using MTCMOS.

References

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Keywords

MTCMOS (Multi threshold CMOS), Sub-threshold leakage current, Vedic Mathematics, Urdhva Tiryagbhyam Sutra.