Call for Paper

CAE solicits original research papers for the July 2021 Edition. Last date of manuscript submission is June 30, 2021.

Read More

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Washington Bhebhe, Michael Opoku Agyeman. Published in Information Sciences.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Washington Bhebhe, Michael Opoku Agyeman
10.5120/cae2016652443

Washington Bhebhe and Michael Opoku Agyeman. A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption. Communications on Applied Electronics 6(3):14-24, November 2016. BibTeX

@article{10.5120/cae2016652443,
	author = {Washington Bhebhe and Michael Opoku Agyeman},
	title = {A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2016},
	volume = {6},
	number = {3},
	month = {Nov},
	year = {2016},
	issn = {2394-4714},
	pages = {14-24},
	numpages = {11},
	url = {http://www.caeaccess.org/archives/volume6/number3/682-2016652443},
	doi = {10.5120/cae2016652443},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

References

  1. Aahn, J., Yoo, S., & Choi, K. (2016). Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. IEEE Transactions on Computers, 65(3), 940–951.
  2. Abadal, S., Mestres, A., Martinez, R., Alarcon, E., Cabellos-Aparicio, A., & Martinez, R. (2015). Multicast On-chip Traffic Analysis Targeting Manycore NoC Design. In 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (pp. 370–378). IEEE
  3. Aneesh Kumar, A. G., Janeera, D. A., & Ramesh, M. (2014). Power and performance efficient secondary cache using tag bloom architecture. In 2014 International Conference on Electronics and Communication Systems (ICECS) (pp. 1–5). IEEE.
  4. Andersen, T., Krismer, F., Kolar, J., Toifl, T., Menolfi, C., Kull, L., … Francese, P. A. (2016). A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery. IEEE Transactions on Power Electronics, 1–1
  5. Arima, E., Noguchi, H., Nakada, T., Miwa, S., Takeda, S., Fujita, S., & Nakamura, H. (2015). Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. In 2015 33rd IEEE International Conference on Computer Design (ICCD) (pp. 149–156).
  6. Arora, N. D., Worley, S., & Ganpule, D. R. (2015). FieldRC, a GPU accelerated interconnect RC parasitic extractor for full-chip designs. In 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) (pp. 459–462). IEEE.
  7. Bardine, A., Comparetti, M., Foglia, P., & Prete, C. A. (2014). Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(1), 185–190.
  8. Bengueddach, A., Senouci, B., Niar, S., & Beldjilali, B. (2013). Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach. In 2013 8th IEEE Design and Test Symposium (pp. 1–6). IEEE.
  9. Cache Simulation Main Page. (n.d.). Retrieved from http://www.ecs.umass.edu/ece/koren/architecture/Cache/frame0.htm
  10. Chakraborty, S., Das, S., & Kapoor, H. K. (2015). Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. In 2015 IEEE International Parallel and Distributed Processing Symposium Workshop (pp. 444–453). IEEE.
  11. Chen, K.-C. J., Chao, C.-H., & Wu, A.-Y. A. (2015). Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managements. IEEE Circuits and Systems Magazine, 15(4), 45–69
  12. Chen, X., Chen, W., Lu, Z., Long, P., Yang, S., & Wang, Z. (2015). A Duplication-Aware SSD-Based Cache Architecture for Primary Storage in Virtualization Environment. IEEE Systems Journal, 1–12.
  13. Cheng, W.-K., Cheng, P.-C., & Li, X.-L. (2016). Adaptive page allocation of DRAM/PCRAM hybrid memory architecture. In 2016 5th International Symposium on Next-Generation Electronics (ISNE) (pp. 1–2). IEEE.
  14. Chien, T.-K., Chiou, L.-Y., Lee, C.-C., Chuang, Y.-C., Ke, S.-H., Sheu, S.-S., … Wu, C.-I. (2016). An energy-efficient nonvolatile microprocessor considering software-hardware interaction for energy harvesting applications. In 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (pp. 1–4). IEEE.
  15. Chenxi Zhang, Xiaodong Zhang, & Yong Yan. (n.d.). Multi-column implementations for cache associativity. In Proceedings International Conference on Computer Design VLSI in Computers and Processors (pp. 504–509). IEEE Comput. Soc.
  16. Choi, M., Jang, T., Bang, S., Shi, Y., Blaauw, D., & Sylvester, D. (2016). A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs. IEEE Journal of Solid-State Circuits, 1–13.
  17. Chung, S. W., & Skadron, K. (2008). On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance. IEEE Transactions on Computers, 57(1), 7–24.
  18. Cilku, B., Prokesch, D., & Puschner, P. (2015). A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking. In 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (pp. 74–79). IEEE
  19. Dai, J., & Wang, L. (2013). An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(1), 102–112.
  20. Datta, A. K., & Patel, R. (2014). CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data. IEEE Transactions on Parallel and Distributed Systems, 25(5), 1190–1199.
  21. De, V. (2015). Fine-grain power management in manycore processor and System-on-Chip (SoC) designs. In 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 159–164). IEEE.
  22. Degnan, B., Marr, B., & Hasler, J. (2016). Assessing Trends in Performance per Watt for Signal Processing Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1), 58–66.
  23. Eeckhout, L. (2015). Hot Chips in an Increasingly Diverse Microprocessor Landscape. IEEE Micro, 35(2), 2–3.
  24. Ezz-Eldin, R., El-Moursy, M. A., & Hamed, H. F. A. (2015). Analysis and design of Network on Chip under high process variation. In 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (pp. 508–509). IEEE.
  25. Farmahini-Farahani, A., Ho Ahn, J., Morrow, K., & Sung Kim, N. (2015). DRAMA: An Architecture for Accelerated Processing Near Memory. IEEE Computer Architecture Letters, 14(1), 26–29.
  26. Fischer, K., Chang, H. ., Ingerly, D., Jin, I., Kilambi, H., Longun, J., … Yashar, P. (2016). Performance enhancement for 14nm high volume manufacturing microprocessor and system on a chip processes. In 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC) (pp. 5–7). IEEE.
  27. Frustaci, F., Corsonello, P., Perri, S., & Cocorullo, G. (n.d.). Leakage energy reduction techniques in deep submicron cache memories: a comparative study. In 2006 IEEE International Symposium on Circuits and Systems (p. 4). IEEE.
  28. Frustaci, F., Corsonello, P., Perri, S., & Cocorullo, G. (n.d.). A New Scheme to Reduce Leakage in DeepSubmicron Cache Memories with No Extra Dynamic Consumption. In 2006 Ph.D. Research in Microelectronics and Electronics (pp. 61–64). IEEE.
  29. Ghaemi, S. G., Monazzah, A. M. H., Farbeh, H., & Miremadi, S. G. (2015). LATED: Lifetime-Aware Tag for Enduring Design. In 2015 11th European Dependable Computing Conference (EDCC) (pp. 97–107). IEEE.
  30. Ghosh, M., & Lee, H.-H. S. (2007). Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems. In 2007 International Conference on Parallel and Distributed Systems (pp. 1–8). IEEE.
  31. Golubeva, O., Loghi, M., Poncino, M., & Macii, E. (2007). Architectural Leakage-Aware Management of Partitioned Scratchpad Memories. In 2007 Design, Automation & Test in Europe Conference & Exhibition (pp. 1–6). IEEE.
  32. Goudarzi, M., Ishihara, T., & Yasuura, H. (2007). A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. In 2007 Asia and South Pacific Design Automation Conference (pp. 878–883). IEEE.
  33. Grani, P., Proietti, R., Cheung, S., & Ben Yoo, S. J. (2016). Flat-Topology High-Throughput Compute Node With AWGR-Based Optical-Interconnects. Journal of Lightwave Technology, 34(12), 2959–2968.
  34. Hameed, F., & Tahoori, M. B. (2016). Architecting STT Last-Level-Cache for performance and energy improvement. In 2016 17th International Symposium on Quality Electronic Design (ISQED) (pp. 319–324). IEEE
  35. Haupt, M., Brunschwiller, T., Keller, J., & Ozsun, O. (2015). Heat transfer modelling of a dual-side cooled microprocessor chip stack with embedded micro-channels. In 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (pp. 1–4). IEEE.
  36. Hu, J. S., Nadgir, A., Vijaykrishnan, N., Irwin, M. J., & Kandemir, M. (n.d.). Exploiting program hotspots and code sequentiality for instruction cache leakage management. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED ’03. (pp. 402–407). ACM
  37. Intel An Overview of Cache Page 2 2.1 Basic Model CPU Cache Memory Main DRAM Memory System Interface. (n.d.).
  38. Isaza-Gonzalez, J., Serrano-Cases, A., Restrepo-Calle, F., Cuenca-Asensi, S., & Martinez-Alvarez, A. (2016). Dependability evaluation of COTS microprocessors via on-chip debugging facilities. In 2016 17th Latin-American Test Symposium (LATS) (pp. 27–32). IEEE.
  39. Jang, H., Kim, J., Gratz, P., Yum, K. H., & Kim, E. J. (2015). Bandwidth-efficient on-chip interconnect designs for GPGPUs. In Proceedings of the 52nd Annual Design Automation Conference on - DAC ’15 (pp. 1–6). New York, New York, USA: ACM Press.
  40. Jing, N., Jiang, L., Zhang, T., Li, C., Fan, F., & Liang, X. (2016). Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs. IEEE Transactions on Computers, 65(1), 122–135.
  41. Jishen Zhao, Xiangyu Dong, & Yuan Xie. (2011). An energy-efficient 3D CMP design with fine-grained voltage scaling. In 2011 Design, Automation & Test in Europe (pp. 1–4). IEEE.
  42. Divya Jebaseeli, A., & Kiruba, M. (2014). Design of low power L2 cache architecture using partial way tag information. In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) (pp. 1–6). IEEE.
  43. Kadjo, D., Kim, H., Gratz, P., Hu, J., & Ayoub, R. (2013). Power gating with block migration in chip-multiprocessor last-level caches. In 2013 IEEE 31st International Conference on Computer Design (ICCD) (pp. 93–99). IEEE
  44. Kalla, P., Xiaobo Sharon Hu, & Henkel, J. (2006). Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(1), 69–80.
  45. Khaitan, S. K., & McCalley, J. D. (2013). A hardware-based approach for saving cache energy in multicore simulation of power systems. In 2013 IEEE Power & Energy Society General Meeting (pp. 1–5). IEEE.
  46. Khaitan, S. K., & McCalley, J. D. (2013). A hardware-based approach for saving cache energy in multicore simulation of power systems. In 2013 IEEE Power & Energy Society General Meeting (pp. 1–5). IEEE.
  47. Kim, C. H., Jae-Joon Kim, Ik-Joon Chang, & Roy, K. (n.d.). PVT-aware leakage reduction for on-die caches with improved read stability. In ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. (pp. 482–484). IEEE.
  48. Kim, C. H., Kim, J.-J., Chang, I.-J., & Roy, K. (2006). PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability. IEEE Journal of Solid-State Circuits, 41(1), 170–178.
  49. Kim, N., Ahn, J., Seo, W., & Choi, K. (2015). Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 183–188). IEEE.
  50. Kudithipudi, D., Petko, S., & John, E. B. (2008). Caches for Multimedia Workloads: Power and Energy Tradeoffs. IEEE Transactions on Multimedia, 10(6), 1013–1021.
  51. Kim, N., Ahn, J., Seo, W., & Choi, K. (2015). Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 183–188). IEEE.
  52. Lee, J., & Kim, S. (2015). Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction. IEEE Transactions on Computers, 64(7), 1927–1939.
  53. Lee, J., Woo, D. H., Kim, H., & Azimi, M. (2015). GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs. IEEE Transactions on Computers, 64(11), 3167–3180.
  54. Lee, S., Kang, K., Jung, J., & Kyung, C.-M. (2016). Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1–14.
  55. Lin, I.-C., & Chiou, J.-N. (2015). High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10), 2149–2161.
  56. Lin, I.-J., Yang, M.-J., & Hu, K.-S. (2016). Single layer differential group routing for flip-chip designs. In 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (pp. 1–4). IEEE.
  57. Lockwood, J. W., & Monga, M. (2016). Implementing Ultra-Low-Latency Datacenter Services with Programmable Logic. IEEE Micro, 36(4), 18–26.
  58. Loghi, M., Golubeva, O., Macii, E., & Poncino, M. (2010). Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking. IEEE Transactions on Computers, 59(7), 891–904.
  59. Lou, M., Wu, L., Shi, S., & Lu, P. (2014). An energy-efficient two-level cache architecture for chip multiprocessors. In Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT) (pp. 1–5). IEEE.
  60. Mallya, N. B., Patil, G., & Raveendran, B. (2015). Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. In 2015 28th International Conference on VLSI Design (pp. 65–70). IEEE.
  61. Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N., & Sugibayashi, T. (2013). Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. In 2013 IEEE 10th International Conference on ASIC (pp. 1–4). IEEE.
  62. Mittal, S., Cao, Y., & Zhang, Z. (2014). MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(8), 1653–1665
  63. Mittal, S., Zhang, Z., & Cao, Y. (2013). CASHIER: A Cache Energy Saving Technique for QoS Systems. In 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (pp. 43–48). IEEE.
  64. Mittal, S. (n.d.). A Survey of Architectural Techniques For Improving Cache Power Efficiency
  65. Mittal, S., Zhang, Z., & Cao, Y. (2013). CASHIER: A Cache Energy Saving Technique for QoS Systems. In 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (pp. 43–48). IEEE.
  66. Mittal, S., Zhang, Z., & Vetter, J. S. (2013). FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration. In 2013 IEEE 31st International Conference on Computer Design (ICCD) (pp. 100–107). IEEE
  67. Mittal, S., Zhang, Z., & Vetter, J. S. (2013). FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration. In 2013 IEEE 31st International Conference on Computer Design (ICCD) (pp. 100–107). IEEE.
  68. Moein, S., Gulliver, T. A., Gebali, F., & Alkandari, A. (2016). A New Characterization of Hardware Trojans. IEEE Access, 4, 2721–2731.
  69. Mohammadi, M., Han, S., Aamodt, T. M., & Dally, W. J. (2015). On-Demand Dynamic Branch Prediction. IEEE Computer Architecture Letters, 14(1), 50–53
  70. Monchiero, M., Canal, R., & Gonzalez, A. (2009). Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. In 2009 International Conference on Parallel Processing (pp. 1–8). IEEE
  71. Nadgir, A., Kandemir, M., Guangyu Chen, & Guilin Chen. (n.d.). An access pattern based energy management strategy for instruction caches. In IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. (pp. 175–178). IEEE.
  72. Ray, A., & Choudhry, A. (2015). Time optimization of instruction execution in FPGA using embedded systems. In 2015 International Conference on Futuristic Trends on Computational Analysis and Knowledge Management (ABLAZE) (pp. 566–572). IEEE.
  73. Rossi, D., Tenentes, V., Khursheed, S., & Al-Hashimi, B. M. (2015). BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. In 2015 IEEE 21st International On-Line Testing Symposium (IOLTS) (pp. 194–199). IEEE.
  74. Sai Manoj, P. D., & Hao Yu. (2013). Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) (pp. 533–536). IEEE.
  75. Sampaio, F., Shafique, M., Zatt, B., Bampi, S., & Henkel, J. (2015). Approximation-aware Multi-Level Cells STT-RAM cache architecture. In 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) (pp. 79–88). IEEE.
  76. Seongmoo Heo, Barr, K., Hampton, M., & Asanovic, K. (n.d.). Dynamic fine-grain leakage reduction using leakage-biased bitlines. In Proceedings 29th Annual International Symposium on Computer Architecture (pp. 137–147). IEEE Comput. Soc.
  77. Shum, C. K., Busaba, F., & Jacobi, C. (2013). IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor. IEEE Micro, 33(2), 38–47.
  78. Soontae Kim, Vijaykrishnan, N., Kandemir, M., & Irwin, M. J. (n.d.). Predictive precharging for bitline leakage energy reduction [microprocessor caches]. In 15th Annual IEEE International ASIC/SOC Conference (pp. 36–40). IEEE.
  79. Subha, S. (2014). A reconfigurable cache architecture. In 2014 International Conference on High Performance Computing and Applications (ICHPCA) (pp. 1–5). IEEE.
  80. Tao Li, & John, L. K. (n.d.). OS-aware Tuning: Improving Instruction Cache Energy Efficiency on System Workloads. In 2006 IEEE International Performance Computing and Communications Conference (pp. 321–330). IEEE
  81. Tsoutsos, N. G., & Maniatakos, M. (2015). The HEROIC Framework: Encrypted Computation Without Shared Keys. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(6), 875–888.
  82. Tu, C.-Y., Chang, Y.-Y., King, C.-T., Chen, C.-T., & Wang, T.-Y. (2014). Traffic-aware frequency scaling for balanced on-chip networks on GPGPUs. In 2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS) (pp. 87–94). IEEE.
  83. Ubal, R., Sahuquillo, J., Petit, S., & Lopez, P. (2006). Applying the zeros switch-off technique to reduce static energy in data caches. In 2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’06) (pp. 133–140). IEEE.
  84. Ubal, R., Sahuquillo, J., Petit, S., Hassan, H., & Lopez, P. (2007). Leakage Current Reduction in Data Caches on Embedded Systems. In The 2007 International Conference on Intelligent Pervasive Computing (IPC 2007) (pp. 45–50). IEEE.
  85. Valero, A., Sahuquillo, J., Petit, S., Lopez, P., & Duato, J. (2015). Design of Hybrid Second-Level Caches. IEEE Transactions on Computers, 64(7), 1884–1897
  86. Wang, W., & Mishra, P. (2010). Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. In 2010 23rd International Conference on VLSI Design (pp. 357–362). IEEE.
  87. Wang, Z., Jimenez, D. A., Xu, C., Sun, G., & Xie, Y. (2014). Adaptive placement and migration policy for an STT-RAM-based hybrid cache. In 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) (pp. 13–24). IEEE.
  88. Warnock, J., Chan, Y. H., Harrer, H., Rude, D., Puri, R., Carey, S., … Webb, C. (2013). 5.5GHz system z microprocessor and multi-chip module. In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 46–47). IEEE.
  89. Warnock, J., Chan, Y., Harrer, H., Carey, S., Salem, G., Malone, D., … Webb, C. (2014). Circuit and Physical Design of the zEnterpriseTM EC12 Microprocessor Chips and Multi-Chip Module. IEEE Journal of Solid-State Circuits, 49(1), 9–18.
  90. Weixun Wang, & Mishra, P. (2012). System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(5), 902–910.
  91. Wu, Y., Zhao, J., Chen, D., & Guo, D. (2016). Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs. IEEE Transactions on Computers, 65(7), 2134–2142.
  92. Xiaoping, H., & Jianfeng, A. (2013). A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit. In 2013 IEEE 16th International Conference on Computational Science and Engineering (pp. 766–769). IEEE.
  93. Yan-Fang, S., Jian-Guo, S., & Yu-Qian, X. (2015). Design and Application of Distributed Intelligent Greenhouse Computerized System. In 2015 Seventh International Conference on Measuring Technology and Mechatronics Automation (pp. 331–334). IEEE.
  94. Yen, C.-H., Chen, C.-H., & Chen, K.-C. (2015). A memory-efficient NoC system for OpenCL many-core platform. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1386–1389). IEEE
  95. Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, & Yuan Xie. (2010). Energy- and endurance-aware design of phase change memory caches. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) (pp. 136–141). IEEE.
  96. Yu, S., & Zhang, W. (2008). Adaptive Drowsy Cache Control for Java Applications. In 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (pp. 185–191). IEEE.
  97. Yue Wang, Roy, S., & Ranganathan, N. (2012). Run-time power-gating in caches of GPUs for leakage energy savings. In 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 300–303). IEEE
  98. Zhang, Q., Li, Z., & Pei, S. (2013). A high performance inter-chip fiber communication scheme with short frame protocol. In 2013 IEEE Third International Conference on Information Science and Technology (ICIST) (pp. 850–853). IEEE.
  99. Sajith, V., & Sobhan, C. B. P. (2012). Characterization of Heat Dissipation From a Microprocessor Chip Using Digital Interferometry. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2(8), 1298–1306.
  100. Gardner, A. T., & Collins, J. A. (2012). Advancements in high-performance timing for long term underwater experiments: A comparison of chip scale atomic clocks to traditional microprocessor-compensated crystal oscillators. In 2012 Oceans (pp. 1–8). IEEE.
  101. Warnock, J., Chan, Y. H., Harrer, H., Rude, D., Puri, R., Carey, S., … Webb, C. (2013). 5.5GHz system z microprocessor and multi-chip module. In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 46–47). IEEE.
  102. Sai Manoj, P. D., & Hao Yu. (2013). Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) (pp. 533–536). IEEE.
  103. Isaza-Gonzalez, J., Serrano-Cases, A., Restrepo-Calle, F., Cuenca-Asensi, S., & Martinez-Alvarez, A. (2016). Dependability evaluation of COTS microprocessors via on-chip debugging facilities. In 2016 17th Latin-American Test Symposium (LATS) (pp. 27–32). IEEE.
  104. Haupt, M., Brunschwiller, T., Keller, J., & Ozsun, O. (2015). Heat transfer modelling of a dual-side cooled microprocessor chip stack with embedded micro-channels. In 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC) (pp. 1–4). IEEE.
  105. Xiaoping, H., & Jianfeng, A. (2013). A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit. In 2013 IEEE 16th International Conference on Computational Science and Engineering (pp. 766–769). IEEE.
  106. Shum, C.-L. (2012). IBM zNext - the 3rd generation high frequency microprocessor chip. In 2012 IEEE Hot Chips 24 Symposium (HCS) (pp. 1–18). IEEE
  107. Zhu, H., & Kursun, V. (2014). Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages. In 2014 26th International Conference on Microelectronics (ICM) (pp. 176–179). IEEE.

Keywords

Fetching; Power Gating; Immediate Sleep; Dynamic and Leakage.