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An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic

Rohini Hongal, Jyoti H, Rajashekar S. Published in Security.

Communications on Applied Electronics
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Rohini Hongal, Jyoti H, Rajashekar S

Rohini Hongal, Jyoti H and Rajashekar S. An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic. Communications on Applied Electronics 7(22):7-13, November 2018. BibTeX

	author = {Rohini Hongal and Jyoti H and Rajashekar S},
	title = {An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2018},
	volume = {7},
	number = {22},
	month = {Nov},
	year = {2018},
	issn = {2394-4714},
	pages = {7-13},
	numpages = {7},
	url = {},
	doi = {10.5120/cae2018652793},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


The main aim of this paper is to provide higher security for several applications over the Internet by enhancing the overall strength of the existing Advanced Encryption Standard algorithm (AES). The standard AES uses block size of 128-bit and key sizes of 128, 192, 256 bits. AES is the most popular ,highly secure, faster and strong symmetric key, block cipher cryptographic algorithm today . But in nowadays, cyber-attacks are continuously developing. Shannon’s theorem states that a one-on-one relationship between each message bit to each key bit (hence both key and message length equal) would give the best security. To improve the security of the original AES, message size is increased from standard block size of 128 bits to 192,256, 512 bits and key size is made as equal as the message block size. We get more security by the use of larger key size and the increased throughput from the larger input block size compared to original AES of 128 bits. The implementation of proposed algorithm require more area but it can be accepted as most of the applications require high level of security and high throughput. Further, paper discusses the use of reversible logic to mitigate the power attacks in conventional AES as reversible gates offer ideally zero internal power dissipation. The proposed work is designed and implemented using Xilinx tool and verified on Virtex-5 FPGA using chipscope. Results are discussed w.r.t power, delay and hardware required in terms of gate count is calculated and implemented using only Feynman gate with quantum cost 1.


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Chipscope, FPGA, Reversible gates, Symmetric key, Quantum Cost.