Call for Paper

CAE solicits original research papers for the July 2023 Edition. Last date of manuscript submission is June 30, 2023.

Read More

An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic

Rohini Hongal, Jyoti H, Rajashekar S. Published in Security.

Communications on Applied Electronics
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Rohini Hongal, Jyoti H, Rajashekar S

Rohini Hongal, Jyoti H and Rajashekar S. An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic. Communications on Applied Electronics 7(22):7-13, November 2018. BibTeX

	author = {Rohini Hongal and Jyoti H and Rajashekar S},
	title = {An Approach towards Design of N-Bit AES to Enhance Security using Reversible Logic},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2018},
	volume = {7},
	number = {22},
	month = {Nov},
	year = {2018},
	issn = {2394-4714},
	pages = {7-13},
	numpages = {7},
	url = {},
	doi = {10.5120/cae2018652793},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


The main aim of this paper is to provide higher security for several applications over the Internet by enhancing the overall strength of the existing Advanced Encryption Standard algorithm (AES). The standard AES uses block size of 128-bit and key sizes of 128, 192, 256 bits. AES is the most popular ,highly secure, faster and strong symmetric key, block cipher cryptographic algorithm today . But in nowadays, cyber-attacks are continuously developing. Shannon’s theorem states that a one-on-one relationship between each message bit to each key bit (hence both key and message length equal) would give the best security. To improve the security of the original AES, message size is increased from standard block size of 128 bits to 192,256, 512 bits and key size is made as equal as the message block size. We get more security by the use of larger key size and the increased throughput from the larger input block size compared to original AES of 128 bits. The implementation of proposed algorithm require more area but it can be accepted as most of the applications require high level of security and high throughput. Further, paper discusses the use of reversible logic to mitigate the power attacks in conventional AES as reversible gates offer ideally zero internal power dissipation. The proposed work is designed and implemented using Xilinx tool and verified on Virtex-5 FPGA using chipscope. Results are discussed w.r.t power, delay and hardware required in terms of gate count is calculated and implemented using only Feynman gate with quantum cost 1.


  1. Srinivas, NS Sai, and Md Akramuddin. "FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption." Electrical, Electronics, and Optimization Techniques (ICEEOT), International Conference on. IEEE, 2016.
  2. Nag, K. Sowmya, H. B. Bhuvaneswari, and A. C. Nuthan. "Implementation of advanced encryption Standard-192 bit using multiple keys." (2013): 2-26.
  3. Jonwal, Sheetal U., and Pratibha P. Shingare. "Advanced Encryption Standard (AES) implementation on FPGA with hardware in loop." Trends in Electronics and Informatics (ICEI), 2017 International Conference on. IEEE, 2017.
  4. Raj, Gaurav, Ram Charan Kesireddi, and Shruti Gupta. "Enhancement of security mechanism for confidential data using AES-128, 192 and 256bit encryption in cloud." Next Generation Computing Technologies (NGCT), 2015 1st International Conference on. IEEE, 2015.
  5. D'souza, Flevina Jonese, and Dakshata Panchal. "Advanced encryption standard (AES) security enhancement using hybrid approach." Computing, Communication and Automation (ICCCA), 2017 International Conference on. IEEE, 2017.
  6. Saicheur, Vatchara, and Krerk Piromsopa. "An implementation of AES-128 and AES-512 on Apple mobile processor." Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2017 14th International Conference on. IEEE, 2017.
  7. Moh'd, Abidalrahman, Yaser Jararweh, and Lo'ai Tawalbeh. "AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation." Information Assurance and Security (IAS), 2011 7th International Conference on. IEEE, 2011.
  8. Saberi, Iman, Bahareh Shojaie, and Mazleena Salleh. "Enhanced key expansion for AES-256 by using even-odd method." Research and Innovation in Information Systems (ICRIIS), 2011 International Conference on. IEEE, 2011.
  9. H Rohini, Rajashekar,P Kumar: Design of basic sequential circuits using reversible logic. International conference on electrical, electronics, and optimization techniques(ICEEOT),March 2016, pp.2110-2115.
  10. Rohini H, Rajashekar S: Design of Reversible logic based combinational circuits. Communications on Applied Electronics (CAE),Sept 2016, Vol 5, pp. 38-43.
  11. Rohini S H, Jyoti R H, Rajashekar B. S: Reversible Logic Based Modified Design of AES-CBC Mode. Seventh International conference on Advanced electrica Measurement & instrumentation Engineering (EMIE), 13,14 July 2018, pp.171-176.
  12. Rohini S. H, Nikhita M, Pooja A, Rajashekar B. S: Performance Analysis of AES-128bits,192bits & 256bits using reversible logic. Seventh International conference on Advanced electrica Measurement & instrumentation Engineering (EMIE), 13,14 July 2018, pp.165-170.


Chipscope, FPGA, Reversible gates, Symmetric key, Quantum Cost.