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Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL)

Ranjith K. G., Arunkumar P. Chavan, H. V. Ravish Aradhya. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2017
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Ranjith K. G., Arunkumar P. Chavan, H. V. Ravish Aradhya
10.5120/cae2017652648

Ranjith K G., Arunkumar P Chavan and Ravish H V Aradhya. Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL). Communications on Applied Electronics 7(4):39-43, July 2017. BibTeX

@article{10.5120/cae2017652648,
	author = {Ranjith K. G. and Arunkumar P. Chavan and H. V. Ravish Aradhya},
	title = {Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL)},
	journal = {Communications on Applied Electronics},
	issue_date = {July 2017},
	volume = {7},
	number = {4},
	month = {Jul},
	year = {2017},
	issn = {2394-4714},
	pages = {39-43},
	numpages = {5},
	url = {http://www.caeaccess.org/archives/volume7/number4/752-2017652648},
	doi = {10.5120/cae2017652648},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Sub-threshold Adiabatic Logic (SAL) is a power saving technique used in VLSI circuit design for applications where power saving is of primary importance. An 8-Bit ALU is designed and implemented based on Sub-Threshold Adiabatic Logic (SAL) using Cadence 45nm technology node. Initially basic blocks decoder, adder and multiplexer are designed and tested for their functionality. Designed basic blocks are integrated to design 8-Bit ALU. Designed ALU is simulated for different inputs to check its functionality. Propagation delay, average power delivered by source, and Power Delay Product (PDP) are computed to compare with CMOS implementation of ALU. A 40db improvement in relative power consumed is observed in SAL compared to CMOS logic. Physical design of the ALU is built to compute chip area of the designed ALU and the total chip area observed is 32,190 um2 with area utilization of 89%.

References

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  2. Dr. H V Ravish Aradhya, et al, “Sub-threshold Adiabatic Logic(SAL) based building blocks for combinational system design” in RTEICT-2017, Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017.
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Keywords

Sub threshold Adiabatic Logic (SAL), Low power, ALU.