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Study of FinFET based Circuit for Ultra-Low Power Operation

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Manisha Guduri, Shruti Agrawal, Vikash Kumar, Aminul Islam Published in Circuit And Systems

Study of FinFET based Circuit for Ultra-Low Power Operation
CAE Proceedings on International Conference on Computing, Communication and Sensor Network
Year of Publication: 2016
© 2015 by CAE Journal
Series CCSN2015 Number 1
Authors Manisha Guduri, Shruti Agrawal, Vikash Kumar, Aminul Islam
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Manisha Guduri, Shruti Agrawal, Vikash Kumar and Aminul Islam. Article: Study of FinFET based Circuit for Ultra-Low Power Operation. CAE Proceedings on International Conference on Computing, Communication and Sensor Network CCSN 2015(1):25-28, March 2016. Published by Foundation of Computer Science, New York, USA. BibTeX

@article{key:article,
	author = {Manisha Guduri and Shruti Agrawal and Vikash Kumar and Aminul Islam},
	title = {Article: Study of FinFET based Circuit for Ultra-Low Power Operation},
	journal = {CAE Proceedings on International Conference on Computing, Communication and Sensor Network},
	year = {2016},
	volume = {CCSN 2015},
	number = {1},
	pages = {25-28},
	month = {March},
	note = {Published by Foundation of Computer Science, New York, USA}
}

Abstract

This work aims at analysing leakage power and its variability of CMOS and FinFET inverter chain at 32-nm technology node. This paper also analyses other design metrics like propagation delay, power-delay product (PDP) and energy-delay product (EDP) of CMOS based inverter and FinFET based inverter. FinFET based inverter design achieves 1. 58× (1. 32×), 10. 03×, 4. 71× 5. 11× improvement in leakage power (its variability), propagation delay, PDP and EDP respectively compared to its CMOS based inverter. In this analysis the FinFET based inverter is found to be suitable for ultra-low power applications like portable and wearable devices.

References

  1. Qing Xie; Xue Lin; Yanzhi Wang; Shuang Chen; Dousti, M. J. ; Pedram, M. , "Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries," in Circuits and Systems II: Express Briefs, IEEE Transactions on , vol. 62, no. 8, pp. 761-765, Aug. 2015.
  2. Hu, V. P. -H. ; Ming-Long Fan; Pin Su; Ching-Te Chuang, "Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist," in Electron Devices, IEEE Transactions on , vol. 62, no. 6, pp. 1710-1715, June 2015.
  3. Ming-Long Fan; Yu-Sheng Wu; Hu, V. P. -H. ; Pin Su; Ching-Te Chuang, "Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model," in Electron Devices, IEEE Transactions on , vol. 57, no. 6, pp. 1375-1381, June 2010.
  4. Kerber, P. ; Kanj, R. ; Joshi, R. V. , "Strained SOI FINFET SRAM Design," in Electron Device Letters, IEEE , vol. 34, no. 7, pp. 876-878, July 2013.
  5. Hu, V. P. -H. ; Ming-Long Fan; Pin Su; Ching-Te Chuang, "Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET," in Electron Devices, IEEE Transactions on , vol. 60, no. 10, pp. 3596-3600, Oct. 2013.
  6. Soon-Gyu Kwon; Jin-Woo Han; Choi, Yang-Kyu, "A Bendable-Channel FinFET for Logic Application," in Electron Device Letters, IEEE , vol. 31, no. 6, pp. 624-626, June 2010.
  7. Alioto, M. , "Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 19, no. 5, pp. 751-762, May 2011.
  8. Peng Zheng; Connelly, D. ; Fei Ding; Tsu-Jae King Liu, "Simulation-Based Study of the Inserted-Oxide FinFET for Future Low-Power System-on-Chip Applications," in Electron Device Letters, IEEE , vol. 36, no. 8, pp. 742-744, Aug. 2015.
  9. Raj, B. ; Saxena, A. K. ; Dasgupta, S. , "Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect," in Circuits and Systems Magazine, IEEE , vol. 11, no. 3, pp. 38-50, third quarter 2011.
  10. M. Morris Mano, Michel D. Ciletti, "Digital Design, Fourth Edition". Prentice Hall of India (PHI), New Delhi, 2008.
  11. John F Wakerly, "Digital Design, Principles and Practices", Third edition, Prentice Hall.
  12. Gruebler, A. ; Suzuki, K. , "Design of a Wearable Device for Reading Positive Expressions from Facial EMG Signals," Affective Computing, IEEE Transactions on , vol. 5, no. 3, pp. 227,237, July-Sept. 1 2014.
  13. Hong Zhang; Yuecheng Li; Hackworth, S. A. ; Yaofeng Yue; Chengliu Li; Guifang Yan; Mingui Sun, "The design and realization of a wearable embedded device for dietary and physical activity monitoring," Systems and Control in Aeronautics and Astronautics (ISSCAA), 2010, vol. , no. , pp. 123,126,8-10 June2010.
  14. Guduri, M. ; Islam, A. , "Design of hybrid full adder in deep subthreshold region for ultralow power applications," SPIN, 2015, pp. 931-935, 19-20 Feb. 2015.
  15. Srivastava, P. ; Dwivedi, A. K. ; Islam, A. , "Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime," in Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on , vol. , no. , pp. 440-444, 8-10 May 2014.
  16. Islam, A. ; Akram, M. W. ; Hasan, M. , "Variability Immune FinFET-Based Full Adder Design in Subthreshold Region," in Devices and Communications (ICDeCom), 2011 International Conference on , vol. , no. , pp. 1-5, 24-25 Feb. 2011.
  17. Pandey, A. ; Raycha, S. ; Maheshwaram, S. ; Manhas, S. K. ; Dasgupta, S. ; Saxena, A. K. ; Anand, B. , "Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances," in Electron Devices, IEEE Transactions on , vol. 61, no. 1, pp. 30-36, Jan. 2014.
  18. Islam, A. ; Imran, A. ; Hasan, M. , "Variability analysis and FinFET-based design of XOR and XNOR circuit," in Computer and Communication Technology (ICCCT), 2011 2nd International Conference on , vol. , no. , pp. 239-245, 15-17 Sept. 2011.
  19. Xiaoxia Wu; Feng Wang; Yuan Xie, "Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design," in SOC Conference, 2006 IEEE International , vol. , no. , pp. 91-92, 24-27 Sept. 2006.
  20. J. Kim, and K. Roy, "Double Gate-MOSFET Subthreshold Circuit for Ultralow Power Applications," IEEE Trans. Electron Devices, vol. 51 (9), pp. 1468-1474, 2004.
  21. X. Huang, W. -C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. -K. Choi, K. Asano, V. Subramanian, T. -J. King, J. Boker, and C. Hu, "Sub 50nm FinFET: PMOS," Int. Electron Devices Meeting Tech. Dig. , Washington DC, 1999, pp. 67-70.
  22. He, F. ; Xingye Zhou; Chenyue Ma; Jian Zhang; Zhiwei Liu; Wen Wu; Xukai Zhang; Lining Zhang, "FinFET: From compact modeling to circuit performance," inElectron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of , vol. , no. , pp. 1-6, 15-17 Dec. 2010
  23. Ming-Long Fan; Yu-Sheng Wu; Hu, V. P. -H. ; Pin Su; Ching-Te Chuang, "Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model," in Electron Devices, IEEE Transactions on , vol. 57, no. 6, pp. 1375-1381, June 2010.

Keywords

Leakage Power, variability; power-delay product (PDP); energy-delay product (EDP); ultralow-power design.