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Combined Architecture for AES Encryption and Decryption using FPGA

Poonam Kadam, Nilima D. Parmar Published in Security

CAE Proceedings on International Conference on Communication Technology
Year of Publication: 2016
© 2015 by CAE Journal

Poonam Kadam and Nilima D Parmar. Article: Combined Architecture for AES Encryption and Decryption using FPGA. CAE Proceedings on International Conference on Communication Technology ICCT 2015(2):14-17, February 2016. Published by Foundation of Computer Science, New York, USA. BibTeX

@article{key:article,
	author = {Poonam Kadam and Nilima D. Parmar},
	title = {Article: Combined Architecture for AES Encryption and Decryption using FPGA},
	journal = {CAE Proceedings on International Conference on Communication Technology},
	year = {2016},
	volume = {ICCT 2015},
	number = {2},
	pages = {14-17},
	month = {February},
	note = {Published by Foundation of Computer Science, New York, USA}
}

Abstract

This paper presents a combined architecture of Advanced Encryption Standard-128 encryption and decryption for high speed application. A select line named enc/dec is used to select either of the two operations. If enc/dec is 0, then encryption will take place and if it's 1 then decryption. Pipelining and sub-pipelining is used to enhance the speed of operation. Use of 9 stage sub-pipelining per round unit gives a throughput of 18. 773 Gbps on Xilinx Virtex XCV3200E-8-BG560 device whereas it gives a throughput of 24. 930 Gbps on SPARTAN 3 XC3S4000-5fg676 device.

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Keywords

AES; Rijndael; pipelining; encryption; decryption