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Structural Analysis of Efficient Error Control Scheme in PLC Environment

Zaveri Himani, Vala Brijesh Published in Information Sciences

Communications on Applied Electronics
Year of Publication: 2015
© 2014 by CAE Journal
10.5120/cae-1532

Zaveri Himani and Vala Brijesh. Article: Structural Analysis of Efficient Error Control Scheme in PLC Environment. Communications on Applied Electronics 1(3):29-32, February 2015. Published by Foundation of Computer Science, New York, USA. BibTeX

@article{key:article,
	author = {Zaveri Himani and Vala Brijesh},
	title = {Article: Structural Analysis of Efficient Error Control Scheme in PLC Environment},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {1},
	number = {3},
	pages = {29-32},
	month = {February},
	note = {Published by Foundation of Computer Science, New York, USA}
}

Abstract

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their better performance, specially at low Signal-to-Noise Ratio (SNR) as are common in Powerline channels. Turbo Code is patented hence it is costlier for HomePlug device so it cannot be used. For small block length other code like LDPC which gives better performance as Turbo Code but at low SNR. Complexity of LDPC is increased when block length increase and it works well with low code rate. Complexity of Polar code is not increase even though its block length increases. The objective of this paper is to implement Polar code on PLC Channel to reduce the complexity and improve BER using specific Block Length.

Reference

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Keywords

PLC, Code rate, Complexity