|Communications on Applied Electronics|
|Foundation of Computer Science (FCS), NY, USA|
|Volume 2 - Number 2|
|Year of Publication: 2015|
|Authors: Sara M. Hassan, Abdelhalim Zekry|
Sara M. Hassan, Abdelhalim Zekry . FPGA Implementation of LTE Downlink Transceiver with Synchronization and Equalization. Communications on Applied Electronics. 2, 2 ( June 2015), 1-11. DOI=10.5120/cae-1663
Long Term Evolution (LTE) is an advanced standard of the mobile communication systems. LTE has been developed by the 3rd Generation Partnership Project (3GPP). The new features exhibited by LTE is a direct impact of applying new modulation and coding techniques such as the Orthogonal Frequency Division Multiplexing (OFDM) for the Downlink and the Single Carrier Frequency Division Multiple Access (SC-FDMA) for the Uplink as well as turbo coding. This paper presents a Field Programmable Gate Array (FPGA) design and implementation of the LTE downlink transmitter and receiver according to releases 8 and 9 on Virtex 6 XC6VLX240T FPGA kit using Xilinx® ISE® Design Suite version 12. 1. It is found that the utilization of the look up tables and flip plops amounts to about 65 percent while the other logic devices utilization on the chip amount to only 5-13 percent. Such implementations can be considered as IPs for software defined radios. The information is also useful for the FPGA developers. The most important consequence is that the FPGA vendors may produce more appropriate counts of the resource blocks for better the utilization of the chips used in the LTE transceivers.