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Low Complexity Farrow Differential Channelizer Algorithm

Temidayo Otunniyi, Adedotun O. Owojori, Erastus O. Ogunti, Akinlolu A. Ponnle Published in Algorithms

Communications on Applied Electronics
Year of Publication: 2015
© 2015 by CAE Journal
10.5120/cae-1571

Temidayo Otunniyi, Adedotun O.owojori, Erastus O Ogunti and Akinlolu A Ponnle. Article: Low Complexity Farrow Differential Channelizer Algorithm. Communications on Applied Electronics 1(6):36-42, April 2015. Published by Foundation of Computer Science, New York, USA. BibTeX

@article{key:article,
	author = {Temidayo Otunniyi and Adedotun O.owojori and Erastus O. Ogunti and Akinlolu A. Ponnle},
	title = {Article: Low Complexity Farrow Differential Channelizer Algorithm},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {1},
	number = {6},
	pages = {36-42},
	month = {April},
	note = {Published by Foundation of Computer Science, New York, USA}
}

Abstract

Reduction in hardware complexities is vital in communication. The major contribution to hardware complexity in many technologies is the multiplier utilized. This work present a proposed algorithm based on Farrow differential polynomial interpolation. This interpolator filter is a time varying poly-phase filter that uses fractional delay to reduce the integer sampling rates to fractional rates. It is a novel polynomial interpolator with less multiplier usage and inherent linear phase low pass filter. The digitized intermediate frequency (IF) by ADC is derived from mixing the signal RF with a local oscillator signal of a given fixed/variable frequency. Digitization using an analog to digital converter (ADC) capable of running at a sampling time of greater or twice the IF with maximum dynamic range of 100 MHz [This is contrary to the direct down conversion of multiband RF to band pass signals where under sampling is used. The algorithm was designed using Altera Digital Signal Processing tool box in MATLAB/ Simulink environment. When implemented it leads to reduction in the computational complexity, power consumption and silicon area. It also showed that a power gain of -15 dBm was observed as output for the GSM channel when compared with the existing modified farrow algorithms which have power gain of -9. 4dBm and farrow polynomial algorithms with power gain of 10. 59dBm. The decimation factor of 260 for a frequency range of 270. 70 kHz was used. Thus a remarkable lower power gain, lower complexity and lower power consumption in mobile system was obtained when compared to farrow polynomial algorithm and modified farrow algorithm.

Reference

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Keywords

Farrow Differential algorithm, Channelization, Multirate Digital Filter Bank, Software Defined Radio, Digital Down Conversion