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An improved Neural Network Design with Asynchronous Programmable Synaptic Memory

Vaishnavi. M, M. Jayasheela Published in Circuits And Systmes

Communications on Applied Electronics
Year of Publication: 2015
© 2015 by CAE Journal

Vaishnavi.m and M.jayasheela. Article: An improved Neural Network Design with Asynchronous Programmable Synaptic Memory. Communications on Applied Electronics 1(7):1-6, May 2015. Published by Foundation of Computer Science, New York, USA. BibTeX

	author = {Vaishnavi.m and M.jayasheela},
	title = {Article: An improved Neural Network Design with Asynchronous Programmable Synaptic Memory},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {1},
	number = {7},
	pages = {1-6},
	month = {May},
	note = {Published by Foundation of Computer Science, New York, USA}


The electrophysiological behavior of real neurons is emulated by the silicon neuron. The network of neurons helps to obtain accurate results for a complicated system which has a non-linear behavior. The network is integrated on a single VLSI device and implemented in various fields as Neural Network. Neural Network is comprises of Asynchronous circuit, Memory architecture, Neuron, and Synapse circuits. The fast access, connectivity and power hungry operation are based on the Asynchronous and memory circuits. Since the power consumption has become a major limiting factor in any VLSI design, the proposed work presents an efficient Neural Network Architecture whose power consumption is minimized by differential and symmetrical properties of the modified C-element in the controller and 10T SRAM cell in the memory Architecture respectively.


  1. An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory Saber Moradi, Student Member, IEEE, and Giacomo Indiveri, Senior Member, IEEE 1932-4545/$31. 00 © 2013 IEEE
  2. C. Mead, Analog VLSI and Neural systems. Reading, MA: Addison- Wesley, 1989.
  3. M. Mahowald and R. Douglas, "A silicon neuron," Nature, vol. 354, pp. 515–518, 1991.
  4. A. van Schaik, "Building blocks for electronic spiking neural networks," Neural Networks, vol. 14, no. 6–7, pp. 617–628, Jul–Sep 2001.
  5. K. Hynna and K. Boahen, "Space–rate coding in an adaptive silicon neuron," Neural Networks, vol. 14, pp. 645–656, 2001.
  6. G. Indiveri, "A low-power adaptive integrate-and-fire neuron circuit," in Proc. IEEE International Symposium on Circuits and Systems. IEEE, May 2003, pp. IV–820–IV–823.
  7. L. Alvado, J. Tomas, S. Saighi, S. Renaud-Le Masson, T. Bal, A. Destexhe, and G. Le Masson, "Hardware computation of conductance-based neuron models," Neurocomputing, vol. 58–60, pp. 109–115, 2004.
  8. M. Simoni, G. Cymbalyuk, M. Sorensen, and S. Calabrese, R. L. De- Weerth, "A multiconductance silicon neuron with biologically matched dynamics," IEEE Transactions on Biomedical Engineering, vol. 51, no. 2, pp. 342–354, February 2004.
  9. J. Schemmel, K. Meier, and E. Mueller, "A new VLSI model of neural microcircuits including spike time dependent plasticity," in Proceedings of the IEEE International Joint Conference on Neural Networks, vol. 3. IEEE, July 2004, pp. 1711–1716.
  10. J. Arthur and K. Boahen, "Recurrently connected silicon neurons with active dendrites for one-shot learning," in IEEE International Joint Conference on Neural Networks, vol. 3, July 2004, pp. 1699–1704.
  11. E. Farquhar and P. Hasler, "A bio-physically inspired silicon neuron," IEEE Transactions on Circuits and Systems???I, vol. 52, no. 3, pp. 477– 488, March 2005.
  12. K. M. Hynna and K. Boahen, "Neuronal ion-channel dynamics in silicon," in 2006 IEEE International Symposium on Circuits and Systems, May 2006, pp. 3614–3617.
  13. J. Arthur and K. Boahen, "Synchrony in silicon: The gamma rhythm," IEEE Transactions on Neural Networks, vol. 18, pp. 1815–1825, 2007.
  14. J. Wijekoon and P. Dudek, "Compact silicon neuron circuit with spiking and bursting behaviour," Neural Networks, vol. 21, no. 2–3, pp. 524–534, March–April 2008.
  15. M. Singh and S. Nowick, "High-throughput asynchronous pipelines for fine-grain dynamic datapaths," in Proc. IEEE 6th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 198–209.
  16. C-element - Wikipedia, the free encyclopedia en. wikipedia. org/wiki/C-element.


Asynchronous, circuit, neural network, static random access memory (SRAM), very large scale integration (VLSI)