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Reseach Article

An improved Neural Network Design with Asynchronous Programmable Synaptic Memory

by Vaishnavi.m, M.jayasheela
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 1 - Number 7
Year of Publication: 2015
Authors: Vaishnavi.m, M.jayasheela
10.5120/cae-1578

Vaishnavi.m, M.jayasheela . An improved Neural Network Design with Asynchronous Programmable Synaptic Memory. Communications on Applied Electronics. 1, 7 ( May 2015), 1-6. DOI=10.5120/cae-1578

@article{ 10.5120/cae-1578,
author = { Vaishnavi.m, M.jayasheela },
title = { An improved Neural Network Design with Asynchronous Programmable Synaptic Memory },
journal = { Communications on Applied Electronics },
issue_date = { May 2015 },
volume = { 1 },
number = { 7 },
month = { May },
year = { 2015 },
issn = { 2394-4714 },
pages = { 1-6 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume1/number7/341-1578/ },
doi = { 10.5120/cae-1578 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-09-04T18:37:46.103560+05:30
%A Vaishnavi.m
%A M.jayasheela
%T An improved Neural Network Design with Asynchronous Programmable Synaptic Memory
%J Communications on Applied Electronics
%@ 2394-4714
%V 1
%N 7
%P 1-6
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The electrophysiological behavior of real neurons is emulated by the silicon neuron. The network of neurons helps to obtain accurate results for a complicated system which has a non-linear behavior. The network is integrated on a single VLSI device and implemented in various fields as Neural Network. Neural Network is comprises of Asynchronous circuit, Memory architecture, Neuron, and Synapse circuits. The fast access, connectivity and power hungry operation are based on the Asynchronous and memory circuits. Since the power consumption has become a major limiting factor in any VLSI design, the proposed work presents an efficient Neural Network Architecture whose power consumption is minimized by differential and symmetrical properties of the modified C-element in the controller and 10T SRAM cell in the memory Architecture respectively.

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Index Terms

Computer Science
Information Sciences

Keywords

Asynchronous circuit neural network static random access memory (SRAM) very large scale integration (VLSI)