|Communications on Applied Electronics|
|Foundation of Computer Science (FCS), NY, USA|
|Volume 4 - Number 6|
|Year of Publication: 2016|
|Authors: Kavitha V., K.V. Ramakrishanan|
Kavitha V., K.V. Ramakrishanan . Performance Enhancement Technique in Multiprocessors. Communications on Applied Electronics. 4, 6 ( March 2016), 23-26. DOI=10.5120/cae2016652118
Design of a programmable Multi core processor to implement compute several complex multimedia applications is presented. The Processor is expected to complete the given task with minimum latency. The hardware must adhere to minimal area and power requirements. This paper gives design details for enhancement of performance parameters of multi core processors. It is necessary to optimize the processor performance at both architectural and execution levels. At architectural level use of locally synchronous clocking mechanism will eliminate the use of global clock tree with the help of asynchronous handshake protocol. At execution level completion time is reduced by 30% with the concept of reconfigurable instruction set processor and parallelism at data, memory, instruction and task level.