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Performance Enhancement Technique in Multiprocessors

by Kavitha V., K.V. Ramakrishanan
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 4 - Number 6
Year of Publication: 2016
Authors: Kavitha V., K.V. Ramakrishanan

Kavitha V., K.V. Ramakrishanan . Performance Enhancement Technique in Multiprocessors. Communications on Applied Electronics. 4, 6 ( March 2016), 23-26. DOI=10.5120/cae2016652118

@article{ 10.5120/cae2016652118,
author = { Kavitha V., K.V. Ramakrishanan },
title = { Performance Enhancement Technique in Multiprocessors },
journal = { Communications on Applied Electronics },
issue_date = { March 2016 },
volume = { 4 },
number = { 6 },
month = { March },
year = { 2016 },
issn = { 2394-4714 },
pages = { 23-26 },
numpages = {9},
url = { },
doi = { 10.5120/cae2016652118 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2023-09-04T19:53:42.777967+05:30
%A Kavitha V.
%A K.V. Ramakrishanan
%T Performance Enhancement Technique in Multiprocessors
%J Communications on Applied Electronics
%@ 2394-4714
%V 4
%N 6
%P 23-26
%D 2016
%I Foundation of Computer Science (FCS), NY, USA

Design of a programmable Multi core processor to implement compute several complex multimedia applications is presented. The Processor is expected to complete the given task with minimum latency. The hardware must adhere to minimal area and power requirements. This paper gives design details for enhancement of performance parameters of multi core processors. It is necessary to optimize the processor performance at both architectural and execution levels. At architectural level use of locally synchronous clocking mechanism will eliminate the use of global clock tree with the help of asynchronous handshake protocol. At execution level completion time is reduced by 30% with the concept of reconfigurable instruction set processor and parallelism at data, memory, instruction and task level.

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Index Terms

Computer Science
Information Sciences


GALS-Globally asynchronous and locally synchronous GPP-General Purpose processors ASIP- Application Specific integrated Protocol ASIC- Application Specific integrated circuits MPSoC- Multi Processor System on chip RISP- Reduced instruction set processor MRPSoC- Multi-Reconfigurable instruction set processor system on chip RFU -Reconfigurable functional unit.