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Reseach Article

Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

by Neha Somra, Kanika Mishra, Ravinder Singh Sawhney
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 2 - Number 7
Year of Publication: 2015
Authors: Neha Somra, Kanika Mishra, Ravinder Singh Sawhney

Neha Somra, Kanika Mishra, Ravinder Singh Sawhney . Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width. Communications on Applied Electronics. 2, 7 ( August 2015), 1-5. DOI=10.5120/cae2015651795

@article{ 10.5120/cae2015651795,
author = { Neha Somra, Kanika Mishra, Ravinder Singh Sawhney },
title = { Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width },
journal = { Communications on Applied Electronics },
issue_date = { August 2015 },
volume = { 2 },
number = { 7 },
month = { August },
year = { 2015 },
issn = { 2394-4714 },
pages = { 1-5 },
numpages = {9},
url = { },
doi = { 10.5120/cae2015651795 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2023-09-04T19:40:18.111848+05:30
%A Neha Somra
%A Kanika Mishra
%A Ravinder Singh Sawhney
%T Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width
%J Communications on Applied Electronics
%@ 2394-4714
%V 2
%N 7
%P 1-5
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor structures. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and 5 nm oxide thickness. We report the drain saturation current is 0.0343453mA at Vg=1V and 0.0410523mA at Vg=1.5V which indicates approximately 20 percent hike in Id with increase in 0.5V gate voltage. We simulate the device for distinct fin thickness from 5 nm to 50 nm. In this thesis we report, for 32 nm gate length FinFET having above 21.33 nm fin width would consequence in short channel effects in spite of having high drain current.

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Index Terms

Computer Science
Information Sciences


CMOS; silicon-on-Insulator (SOI); double-gate; Fin field-effect transistor (FinFET); tues gate; Drain Induced Barrier Lowering (DIBL).