Call for Paper

CAE solicits original research papers for the November 2021 Edition. Last date of manuscript submission is October 30, 2021.

Read More

Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications

M. Rafat M., Mohamed H. El-Mahlawy, A.H. Zaki, M.S. Hamid. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2015
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: M. Rafat M., Mohamed H. El-Mahlawy, A.H. Zaki, M.S. Hamid
10.5120/cae2015651829

Rafat M M., Mohamed H El-Mahlawy, A H Zaki and M S Hamid. Article: Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications. Communications on Applied Electronics 2(8):25-37, September 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {M. Rafat M. and Mohamed H. El-Mahlawy and A.H. Zaki and M.S. Hamid},
	title = {Article: Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {2},
	number = {8},
	pages = {25-37},
	month = {September},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

This paper targets the design of a high dynamic range low-power, low-noise pixel readout integrated circuit (ROIC) that handles the infrared (IR) detector’s output signal of the uncooled thermal IR camera. Throughout the paper, both the optics and the IR detector modules of the IR camera are modeled using the analogue hardware description language (AHDL) to enable extracting the proper input signal required for the ROIC design. A capacitive trans-impedance amplifier (CTIA) is selected for design as a column level ROIC. The core of the CTIA is designed for minimum power consumption by operation in the sub-threshold region. In addition, a design of correlated double sampling (CDS) technique is applied to the CTIA to minimize the noise and the offset levels. The presented CTIA design achieves a power consumption of 5.2μW and root mean square (RMS) output noise of 6.9μV. All the circuits were implemented in 0.13µm CMOS process technology. The design rule check (DRC), layout versus schematic (LVS), parasitic extraction (PE), Process-voltage-temperature (PVT) analysis and post-layout simulation are performed for all designed circuits. The post-layout simulation results illustrate enhancement of the power consumption and noise performance compared to other published ROIC designs. Finally, a new widening dynamic range (WDR) technique is applied to the CTIA with the CDS circuit designs to increase the dynamic range (DR).

References

  1. C.-C. Hsieh, C.-Y. Wu, F.-W. Jih, and T.-P. Sun, "Focal-Plane-Arrays and CMOS ReadoutTechniques of Infrared Imaging Systems," IEEE Transactions on Citcuits and Systems for Video Technology, vol. 7, NO. 4, pp. 594-605, Aug. 1997.
  2. M. Rafat, “CMOS Readout Integrated Circuit Design for Infrared Imagers,” M.Sc. thesis, Military Technical College, Egypt, 2015.
  3. J. F. Johnson and T. S. Lomheim, "Focal-plane signal and noise model–CTIA ROIC," IEEE Transactions on Electron Devices, vol. 56, pp. 2506-2515, Nov. 2009.
  4. A. Ruan, K. Shen, and B. Hu, "Adjustable gain CTIA cell with variable integration time for IRFPA applications," International Conference on Communications, Circuits and Systems (ICCCAS 2009), pp. 1066-1069, July 2009.
  5. F. K. Saleh, "The design and integration of CMOS readout circuitry with an a GexSi1-xOy Cooled Micro-bolometer," master, electronic engineering, carleton, ottawa,ontario,canada, 2007.
  6. Z. Zhu, Y. Yang, and Q. Meng, "A low noise Si-CMOS amplifier-multiplexer readout circuit array for imaging applications," 8th International Conference on Solid-State and Integrated Circuit Technology, ICSICT'06, pp. 629-633, Oct. 2006.
  7. Y. Ha, M. Li, and A. Q. Liu, "A New CMOS Buffer amplifier design used in low voltage MEMS interface circuits," Analog Integrated Circuits and signal processing, vol. 27, pp. 7-17, April 2001.
  8. G. R. Cugler Fiorante, P. Zarkesh-Ha, J. Ghasemi, and S. Krishna, "Spatio-temporal tunable pixels for multi-spectral infrared imagers," in IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS 2013), pp. 317-320, Aug. 2013.
  9. S. Kavusi, K. Ghosh, and A. El Gamal, "Architectures for high dynamic range, high speed image sensor readout circuits" Springer, Nov. 2006.
  10. y.-c. l. tai-Ping Sun, hsiu-li shieh, "A novel readout integrated circuit with a dual-mode design for single- and dual-band infrared focal plane array," el sevier ,infrared physics and technology, March 2013.
  11. J. Lv, Y. Jiang, D. Zhang, and Y. Zhou, "Ultra-low-noise readout integrated circuit for uncooled microbolometers," Electronics letters, vol. 44, pp. June 2008.
  12. S. Kavusi, K. Ghosh, K. Fife, and A. El Gamal, "A 0.18 μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays," IEEE Custom Integrated Circuits Conference, (CICC'06), pp. 229-232, Sept 2006.
  13. C.-C. Hsieh, C.-Y. Wu, F.-W. Jih, T.-P. Sun, and H. Chang, "A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression," IEEE International Symposium on Circuits and Systems, (ISCAS'96), pp. 137-140, May 1996.
  14. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, pp. 1584-1614, Nov 1996.
  15. X. Li, S. Yao, and Y. Zhao, "CMOS readout circuit with new background suppression technique for room-temperature infrared FPA applications," Journal of Circuits, Systems and Signal Processing, vol. 29, NO. 6, pp. 1027-1040, Dec. 2010.
  16. B. Hu, P. Li, and A.-w. Ruan, "A Multifunction snapshot ROIC design for low and high background application," International Conference on Optoelectronics and Image Processing (ICOIP), pp. 44-46, Nov. 2010.
  17. P. L. Bin Hu, Ai-wu Ruan, Dao-ming Lin "Design and verification of 160*120 bolometer ROIC," International Conference on computional problem-solving (ICCP), Oct. 2011.
  18. J. Lv, H. Zhong, Y. Zhou, B. Liao, J. Wang, and Y. Jiang, "Model-Based Low-Noise Readout Integrated Circuit Design for Uncooled Microbolometers," IEEE SENSORS JOURNAL, vol. 13, pp. 1207-1215, April 2013.
  19. R. J. Baker, CMOS: circuit design, layout, and simulation vol. 18: Wiley-IEEE Press, 2011.
  20. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. vol. 7: Oxford University Press, 2002.
  21. D. A. Johns and K. Martin, Analog integrated circuit design: Wiley. com, 2008.
  22. T. Shima, "Temperature insensitive current reference circuit using standard CMOS devices," 50th Midwest Symposium on Circuits and Systems, MWSCAS, pp. 181-184, 2007.
  23. J. Seo, G. Kim, K. Lim, C. Seok, H. Kim, S. Im, J.-H. Kim, C.-Y. Kim, and H. Ko, "An analog front-end IC with regulated RI amplifier and CDS CTIA for microbolometer," 13th International Conference on Control Automation and Systems (ICCAS 2013), pp. 1312-1315, Oct. 2013.
  24. D. Van Blerkom, "Analysis and simulation of CTIA-based pixel reset noise," in SPIE Defense, Security, and Sensing, pp. 80120G-10, May 2011.

Keywords

WDR, CTIA, ROIC, CDS, Thermal imaging