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Modified PFAL Adiabatic Technique for Low Power

Bhakti Patel, Poonam Kadam. Published in Power Systems.

Communications on Applied Electronics
Year of Publication: 2015
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Bhakti Patel, Poonam Kadam
10.5120/cae2015652000

Bhakti Patel and Poonam Kadam. Article: Modified PFAL Adiabatic Technique for Low Power. Communications on Applied Electronics 3(7):40-43, December 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Bhakti Patel and Poonam Kadam},
	title = {Article: Modified PFAL Adiabatic Technique for Low Power},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {3},
	number = {7},
	pages = {40-43},
	month = {December},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

This paper presents the quasi-adiabatic Modified Positive Feedback Adiabatic Logic (MPFAL) for low power operation through energy recovery technique. The circuit of positive feedback adiabatic (PFAL) inverter has been improved here. It is a diode-free and dual rail logic offering both the true and complementary outputs. Validation is done through basic digital gate circuits. Comparison with static CMOS and PFAL circuits are made to prove the designs. In post-layout simulations, energy savings of 27% is achieved against the optimized PFAL Inverter, NAND and NOR gate circuits. The various improvement results are analyzed in LTSPICE tool.

References

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  6. Bhakti Patel, Poonam Kadam, “Comparative Analysis of Adiabatic Logic Techniques”,IJCA,Sept.2015
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Keywords

Static CMOS, PFAL, NAND, NOR