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Performance Enhancement Technique in Multiprocessors

Kavitha V., K.V. Ramakrishanan. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Kavitha V., K.V. Ramakrishanan

Kavitha V. and K V Ramakrishanan. Article: Performance Enhancement Technique in Multiprocessors. Communications on Applied Electronics 4(6):23-26, March 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

	author = {Kavitha V. and K.V. Ramakrishanan},
	title = {Article: Performance Enhancement Technique in Multiprocessors},
	journal = {Communications on Applied Electronics},
	year = {2016},
	volume = {4},
	number = {6},
	pages = {23-26},
	month = {March},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}


Design of a programmable Multi core processor to implement compute several complex multimedia applications is presented. The Processor is expected to complete the given task with minimum latency. The hardware must adhere to minimal area and power requirements. This paper gives design details for enhancement of performance parameters of multi core processors. It is necessary to optimize the processor performance at both architectural and execution levels. At architectural level use of locally synchronous clocking mechanism will eliminate the use of global clock tree with the help of asynchronous handshake protocol. At execution level completion time is reduced by 30% with the concept of reconfigurable instruction set processor and parallelism at data, memory, instruction and task level.


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GALS-Globally asynchronous and locally synchronous, GPP-General Purpose processors, ASIP- Application Specific integrated Protocol, ASIC- Application Specific integrated circuits, MPSoC- Multi Processor System on chip, RISP- Reduced instruction set processor, MRPSoC- Multi-Reconfigurable instruction set processor system on chip, RFU -Reconfigurable functional unit.