Call for Paper

CAE solicits original research papers for the July 2021 Edition. Last date of manuscript submission is June 30, 2021.

Read More

Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor

Shaunak Basu, Subhashree Basu. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Shaunak Basu, Subhashree Basu
10.5120/cae2016652385

Shaunak Basu and Subhashree Basu. Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor. Communications on Applied Electronics 5(10):23-28, September 2016. BibTeX

@article{10.5120/cae2016652385,
	author = {Shaunak Basu and Subhashree Basu},
	title = {Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor},
	journal = {Communications on Applied Electronics},
	issue_date = {September 2016},
	volume = {5},
	number = {10},
	month = {Sep},
	year = {2016},
	issn = {2394-4714},
	pages = {23-28},
	numpages = {6},
	url = {http://www.caeaccess.org/archives/volume5/number10/658-2016652385},
	doi = {10.5120/cae2016652385},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Reversible logic is gaining importance in recent years largely due to its property of low power consumption. It has a wide range of applications which include advance computing, low power CMOS, optical information processing, quantum computing, DNA cryptography and nanotechnology. Reversible gates are the building blocks of quantum computation. This paper presents an optimized parallel binary adder/subtractor using existing reversible gates which is further used to implement a novel circuit capable of performing modulo operation. All circuits have been modeled and verified using Verilog and Modelsim. An overall analysis of the modulo circuit and a comparative study of the proposed parallel adder/subtractor with respect to previous designs in terms of the number of gates, number of garbage outputs and quantum costs is presented.

References

  1. C. Bennett, Logical reversibility of computation, IBM J. Research and Development, vol. 17, no. 6, pp. 525532, Nov. 1973.
  2. T. Toffoli., “Reversible Computing”, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
  3. Himanshu, Thapliyal and M.B Srinivas, ”A beginning in the reversible logic synthesis of sequential circuits having features of online testability”, SPIE Microelectronics, MEMS, and Nanotechnology Symposium, Brisbane, Australia, December 11-14, 2005.
  4. B. Parhami, Fault Tolerant Reversible Circuits Proc. 40th Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, Oct.2006.
  5. Dilip P. Vasudevan, Parag K. Lala, Jia Di and J. Patrick Parkerson, “Reversible Logic Design with Online Testability”, IEEE Transactions on Instrumentation and Measurement, VOL 55, No. 2,April 2006.
  6. M.Mahapatro, S.K.Panda, J.Satpathy,M.Saheel, M.Suresh, A.K.Panda and M.K.Sukla, “Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation”,International Symposium on Electronic System Design (ISED), 2010 pp85 - 90.
  7. Rangaraju H G, Venugopal U, Muralidhara K N, Raja K B, “Low Power Reversible Parallel Binary Adder/Subtractor”. International Journal of VLSI Design & Communication Systems, 1.3(2010),pp-23-34
  8. Shekoofeh Moghimi, Mohammad R. Reshadinezhad “A Novel 4x4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in terms of Reversible and Quantum Metrics”. I.J. Modern Education and Computer Science, 2015, 11, 28-34
  9. Abu Sadat Md. Sayem, Masashi Ueda.”Optimization of reversible sequential circuits”. Journal of Computing, Volume 2, Issue 6, June 2010, ISSN 2151-9617.
  10. Shaunak Basu, Subhashree Basu, “Reversible Logic Synthesis of Sequential Circuits”, International Journal of Computer Applications (0975 – 8887) Volume 129 – No.11, November 2015.
  11. Soolmaz Abbasalizadeh, Behjat Forouzandeh, Hossein Aghababa, “4 Bit Comparator Design Based on Reversible Logic Gates”, Lecture Notes on Information Theory Vol. 1, No. 3, September 2013.
  12. Michael A.Nielsen and Isaac L.Chuang, “Quantum Computation and Quantum Information” 10th Anniversary Edition 2011”.
  13. Md. Belayet Ali, Md. Mosharof Hossin and Md. Eneyat Ullah, “Design of Reversible Sequential Circuit Using Reversible Logic Synthesis”,International Journal of VLSI design and Communication Systems (VLSICS) Vol.2, No.4, December 2011.
  14. Prashant R. Yelekar, Prof. Sujata S. Chiwande, “Introduction to Reversible Logic Gates and its Application”, 2nd National Conference on Information and Communication Technology (NCICT) 2011, Proceedings published in International Journal of Computer Applications(IJCA).
  15. Md. Selim Al Mamun,David Menville.”Quantum Cost Optimization for Reversible Sequential Circuit”, International Journal of Advanced Computer Science and Applications(IJACSA),Vol. 4, No.12, 2013.
  16. T.Ravi, S.Ranjith, V.Kannan.”A Novel Design of D-Flip Flop Using New RR Fault Tolerant Reversible Logic Gate”,International Journal of Emerging Technology and Advanced Engineering(IJETAE), Volume 3, Issue 2, February 2013.
  17. Prashik Lokhande, Jyoti Varavadekar.”Transistor Implementation of D Flip-Flop Using Reversible Logic Circuit”, International Journal of Engineering Research and Technology,Vol. 3 - Issue 4 (April-2014).

Keywords

Reversible logic, Power consumption, CMOS, Nanotechnology, Reversible gates, Modulo operation, Parallel binary adder/subtractor, Garbage Output.