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Reseach Article

Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor

by Shaunak Basu, Subhashree Basu
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 5 - Number 10
Year of Publication: 2016
Authors: Shaunak Basu, Subhashree Basu
10.5120/cae2016652385

Shaunak Basu, Subhashree Basu . Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor. Communications on Applied Electronics. 5, 10 ( Sep 2016), 23-28. DOI=10.5120/cae2016652385

@article{ 10.5120/cae2016652385,
author = { Shaunak Basu, Subhashree Basu },
title = { Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor },
journal = { Communications on Applied Electronics },
issue_date = { Sep 2016 },
volume = { 5 },
number = { 10 },
month = { Sep },
year = { 2016 },
issn = { 2394-4714 },
pages = { 23-28 },
numpages = {9},
url = { https://www.caeaccess.org/archives/volume5/number10/658-2016652385/ },
doi = { 10.5120/cae2016652385 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2023-09-04T19:55:12.931181+05:30
%A Shaunak Basu
%A Subhashree Basu
%T Reversible Logic Synthesis of Modulo Operation using an Optimized Parallel Binary Adder/Subtractor
%J Communications on Applied Electronics
%@ 2394-4714
%V 5
%N 10
%P 23-28
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible logic is gaining importance in recent years largely due to its property of low power consumption. It has a wide range of applications which include advance computing, low power CMOS, optical information processing, quantum computing, DNA cryptography and nanotechnology. Reversible gates are the building blocks of quantum computation. This paper presents an optimized parallel binary adder/subtractor using existing reversible gates which is further used to implement a novel circuit capable of performing modulo operation. All circuits have been modeled and verified using Verilog and Modelsim. An overall analysis of the modulo circuit and a comparative study of the proposed parallel adder/subtractor with respect to previous designs in terms of the number of gates, number of garbage outputs and quantum costs is presented.

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Index Terms

Computer Science
Information Sciences

Keywords

Reversible logic Power consumption CMOS Nanotechnology Reversible gates Modulo operation Parallel binary adder/subtractor Garbage Output.