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A 953nw, 0.8V, 27ppm/⁰C, Nano Power CMOS Voltage Reference Circuit

Dinesh Kushwaha, D. K. Mishra. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Dinesh Kushwaha, D. K. Mishra
10.5120/cae2016652442

Dinesh Kushwaha and D K Mishra. A 953nw, 0.8V, 27ppm/⁰C, Nano Power CMOS Voltage Reference Circuit. Communications on Applied Electronics 6(3):10-13, November 2016. BibTeX

@article{10.5120/cae2016652442,
	author = {Dinesh Kushwaha and D. K. Mishra},
	title = {A 953nw, 0.8V, 27ppm/⁰C, Nano Power CMOS Voltage Reference Circuit},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2016},
	volume = {6},
	number = {3},
	month = {Nov},
	year = {2016},
	issn = {2394-4714},
	pages = {10-13},
	numpages = {4},
	url = {http://www.caeaccess.org/archives/volume6/number3/681-2016652442},
	doi = {10.5120/cae2016652442},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In the field of power-aware applications, like smart sensors, wearable medical devices, required low supply voltage for operation. The supply voltage should be insensitive to temperature variation and line variation and power consumption in order of few micro watts. To achieve this requirements a Nano-power CMOS circuit is designed. It generates a constant reference output voltage working with a supply voltage ranging from 0.8V to 1.8V. Circuit was simulated in 0.18µ

References

  1. A. Wang, B. H. Calhoun, and A. P. Chandracasan, Sub-Threshold Design for Ultra Low-Power Systems. New York: Springer, 2006.
  2. G. De Vita and G. Iannaccone, “A sub-1-V, 10 ppm/ C, nanopowervoltage reference generator,” IEEE J. Solid-State Circuits, vol. 42, no.7, pp. 1536–1542, Jul. 2007.
  3. K. N. Leung and P. K. T. Mol, “A CMOS voltage reference based on weighted_ΔVGS_ for CMOS low-dropout linear regulators,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 146–150, Jan. 2003.
  4. G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutri, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 151–154, Jan. 2003.
  5. K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 ppm/ C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2047–2054, Jul. 2009.
  6. L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 465–474,Feb. 2011.
  7. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997
  8. P.-H. Huang, H. Lin, and Y.-T. Lin, “A simple sub threshold CMOS voltage reference circuit with channel-length modulation compensation,” IEEE Trans. Circuits Syst. II, Expr. Briefs, pp. 882–885, 2006.
  9. B. Razavi, Design of Analog CMOS Integrated Circuits. New York McGraw Hill, 2001, pp. 463–465.
  10. B.S. Song, P.R. Gray, “A precision curvature-compensated CMOS band gap Reference,” IEEE Journal of Solid State Circuits, vol. DC-18, pp.634-643, December 1983.
  11. K.N. Leung, P.K.T. Mok, “A sub-1 V 15 ppm/°C CMOS Band gap Voltage Reference without requiring Low Threshold Voltage Device,”IEEE Journal of Solid State Circuits, vol. 37, pp. 526-530, April 2002.
  12. R.A. Blauschild, P.A. Tucci, R.S. Muller, R.G. Meyer, “A new NMOS Temperature Stable Voltage Reference,” IEEE Journal of Solid State Circuits, vol. SC-13, pp. 767-774, December 1978.
  13. H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, K. Miyazawa“Sub-1 µ A Dynamic Reference Voltage Generator for battery-operated Drams,” IEEE Journal of Solid State Circuits, vol. 29, pp. 448-453,April 1994.
  14. M.C. Tobey, D.J. Gialiani, P.B. As kin, “Flat-Band Voltage Reference”, U.S. Patent 3 975 648, August 1976.
  15. H.J. Oguey, B. Gerber, “MOS Voltage Reference based on polysilicogate work function difference,” IEEEJournal of Solid State Circuit, vol.SC-15, pp. 264-269, June 1980.
  16. K.N. Leung, P.K.T. Mok, K.C. Kwok, “CMOS Voltage Reference,” US Patent 6 441 680, August 2002.

Keywords

Sub threshold, Low power, Low voltage, Power supply rejection ratio, Temperature coefficient,