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Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology

Anjali Sharma, Jyoti Jain. Published in Power Systems.

Communications on Applied Electronics
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Anjali Sharma, Jyoti Jain
10.5120/cae2018652779

Anjali Sharma and Jyoti Jain. Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology. Communications on Applied Electronics 7(19):16-21, August 2018. BibTeX

@article{10.5120/cae2018652779,
	author = {Anjali Sharma and Jyoti Jain},
	title = {Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology},
	journal = {Communications on Applied Electronics},
	issue_date = {August 2018},
	volume = {7},
	number = {19},
	month = {Aug},
	year = {2018},
	issn = {2394-4714},
	pages = {16-21},
	numpages = {6},
	url = {http://www.caeaccess.org/archives/volume7/number19/824-2018652779},
	doi = {10.5120/cae2018652779},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Leakage power reduction has become a major factor in all modern electronic hand held and portable devices due to advancement in the scaling of all Complimentary metal oxide semiconductor devices and circuits. For the reduction of power leakage in the circuit we have used a technique to reduce leakage power at various gates. The approach used here is stack with pass transistor for reduction of leakage power in various gates in the circuit. A parallel combination of NMOS and PMOS transistor is used in parallel for enabling stacking of the transistor for leakage reduction in pull up and pull down network of the transistor. In pull up network NMOS transistor is inserted in parallel to PMOS sacked transistor to maintain Logic level 1. NMOS transistor gets connected to Vdd in pull up Network in sleep mode then pass transistor cut off which achieves a reduction of leakage of 44.63%, 44.63%, 87.02 and 87.44% at 25 Celsius as calculated in two input NAND gate. Also there is a reduction in the Average dynamic power as 15.24%, 15.28%, 35.20%, 31.20% respectively. Area, Delay and Power requirement is satisfied by choosing particular variant of NAND gate. Hence, a trade off is made among these parameters. This technique is also implemented in One bit Full Adder for Low Power leakage design of the circuit.

References

  1. Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, and Alessandro Trifiletti “Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations” IEEE Transactions On Circuits And Systems—I, Vol. 61, No. 2, February 2011.
  2. M Alioto, M Poli, and S Rocchi, “A general power model of differential power analysis attacks to static logic circuits,” IEEE Transaction of Very Large Scale Integration (VLSI) System, volume 18, no. 5, May 2010.
  3. M Alioto, M Poli, and S Rocchi, “Differential power analysis attacks to pre charged buses: a General analysis for symmetric key cryptographic algorithms,” IEEE Trans. Dependable Secure Computation, volume 7, number 3, pages 226– 239, September 2010.
  4. M Alioto, L Giancane, G Scoti, and A Trifileti, “Leakage power analysis attacks: Well defined procedure and first experiment results,” in Proc. International Conference Micro electron. (ICM), pp. 46–49, 2009.
  5. L Lin and W Burleson, “Leakage based differential power analysis (LDPA) on sub 90nanometer CMOS(Complementary metal oxide semiconductor) cryptosystems,” in Proc. IEEE Symp. Circuits Syst (ISCAS), July, 2008.
  6. L Giancane, M Jovanovich, G Scotti, and A Trifiletti, “Leakage power analysis of crypto graphic devices implemented in nano meter CMOS technologies,” IEEE Transactions on circuits and systems, Volume 57, Issue 7, Feb. 2007.
  7. J Giorgetti, G Scotti, A Simonetti, and A Trifiletti, “Analysis of data dependence of the leakage current in CMOS cryptographic hardware,” in Proc Great Lake Symp VLSI (GSLVLSI 2007), Stresa, Italy, March 11, 2007.
  8. G Scotti, M Bucci, R Luzzi, L Giancane, and A Trifiletti, “Delay Based DualRail precharge logic,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, 2011.
  9. M Bucci, L Giancane, R Luzzi, and A Trifiletti, “Three-Phase Dual Rail PreCharge logic,” in Proc. Cryptographic Hardware and Embedded System CHES 2006, 8th Int. Workshop, Lecture Notes in Com- puter Sci. Springer, Yokohama, Japan, Oct. 10–13, 2006.
  10. K Tiri and I Verbauwhede, “A digital design flow for secured integrated circuit,” IEEE Transaction Computer-Aided Design Integration Circuits System volume 25, no. 7, 2006.
  11. K Tiri and I Verbauwhede, “A logic level design methodology for a secure DPA resistant ASIC implementation,” in Proc. Design Automation Test Euro Conference Expo, pp. 246–251, 2004.
  12. S Mangard, E Oswald, and T Pop, Power Analysis Attacks Revealing the Secrets of Smart Cards. New York USA:Springer- Verlag, 2007.
  13. A Abdollahi, F Fallah, and M Pedram, “Leakage current reduction in CMOS circuits by input vector,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, volume 12, number 2, 2004.
  14. L Lin and W P Burleson, “Analysis and mitigation of process variation impact on Power Attack Tolerance,” in Proc Design Automation Conference (DAC), 2009.
  15. T S Messerges, E A Dabbish, and R H Sloan, “Examining smart card security under the threat of power analysis attacks,” IEEE Transaction Computation, volume 51, number 5, 2002.
  16. K Tiri and I Verbauwhede,“Simulation models for side-channel in formation leaks,” in Proc 42nd Design Automation Conference (DAC), Dec 2005.
  17. T Pop and S Mangard, “Masked Dual Rail Precharge logic DPA resistance without routing constraints ,” in Proc. Scotland, UK, volume 3659, Sep. 2005.
  18. H Saputra, N Vijaykrishnan, M Kandemir,Irwin, R Brooks,S Kim, and W Zhang, “Masking the energy behavior of des encryption,” in Proc IEEE Design, Automation Test Europe Conference in the Exhibition, 2003.
  19. K Tiri, M Akmal, I Verbauwhede “A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards,” in Proceedings of the 28th European Solid-State Circuits Conference, 24-26 Sep. 2002.
  20. Md Shazzad Hossain, Ioannis Savidis “Robust near-threshold inverter with improved performance for ultra-low power applications” IEEE International Symposium on Circuits and Systems (ISCAS) 22-25 May 2016.
  21. Lu Liu, Xueqing Li, Vijaykrishnan Narayanan, Suman Datta, “A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors.
  22. C Park and V J Mooney III Sleepy stack leakage reduction, IEEE Transaction VLSI Systems, Volume 14, number 11, pp. 1250-1262, November 2006.
  23. A Keshavarzi, K Roy, and C F Hawkins, Intrinsic leakage in low power deep sub micron CMOS, in Int. Test Conference, 146–155, 1997.

Keywords

Low Power Design, Leakage reduction, Integrated Circuits, VLSI.