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A 3-Bit 10-MSps Low Power CMOS Flash ADC

Andrew Selasi Agbemenu, Ernest Ofosu Addo, Benjamin Kommey. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Andrew Selasi Agbemenu, Ernest Ofosu Addo, Benjamin Kommey
10.5120/cae2018652796

Andrew Selasi Agbemenu, Ernest Ofosu Addo and Benjamin Kommey. A 3-Bit 10-MSps Low Power CMOS Flash ADC. Communications on Applied Electronics 7(22):21-26, November 2018. BibTeX

@article{10.5120/cae2018652796,
	author = {Andrew Selasi Agbemenu and Ernest Ofosu Addo and Benjamin Kommey},
	title = {A 3-Bit 10-MSps Low Power CMOS Flash ADC},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2018},
	volume = {7},
	number = {22},
	month = {Nov},
	year = {2018},
	issn = {2394-4714},
	pages = {21-26},
	numpages = {6},
	url = {http://dev.caeaccess.org/archives/volume7/number22/833-2018652796},
	doi = {10.5120/cae2018652796},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Flash ADCs employ multiple comparator circuits to introduce parallelism in data conversion. Having their speed limited only by transistor gate and comparator propagation delay, flash converters have the fastest signal conversion speeds amongst all ADC architecture implementations. This paper details the design of a low power 3-bit flash ADC with a 3V supply realised in 0.6 micron CMOS technology. The designed ADC exhibits a voltage resolution of 34.13 mV and draws 23.88 mW power at 2.17 MHz.

References

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Keywords

Resistive ladder, Comparators, Bubble noise suppression, Hysteresis