Call for Paper

CAE solicits original research papers for the May 2023 Edition. Last date of manuscript submission is April 30, 2023.

Read More

A 3-Bit 10-MSps Low Power CMOS Flash ADC

SocButtons v1.5

Andrew Selasi Agbemenu, Ernest Ofosu Addo, Benjamin Kommey. Published in Circuits and Systems.

A 3-Bit 10-MSps Low Power CMOS Flash ADC
Communications on Applied Electronics
Year of Publication: 2018
Publisher: Foundation of Computer Science (FCS), NY, USA
Series: Volume 7 Number 22
Authors: Andrew Selasi Agbemenu, Ernest Ofosu Addo, Benjamin Kommey
10.5120/cae2018652796
Download full text

Andrew Selasi Agbemenu, Ernest Ofosu Addo and Benjamin Kommey. A 3-Bit 10-MSps Low Power CMOS Flash ADC. Communications on Applied Electronics 7(22):21-26, November 2018. BibTeX

@article{10.5120/cae2018652796,
	author = {Andrew Selasi Agbemenu and Ernest Ofosu Addo and Benjamin Kommey},
	title = {A 3-Bit 10-MSps Low Power CMOS Flash ADC},
	journal = {Communications on Applied Electronics},
	issue_date = {November 2018},
	volume = {7},
	number = {22},
	month = {Nov},
	year = {2018},
	issn = {2394-4714},
	pages = {21-26},
	numpages = {6},
	url = {http://dev.caeaccess.org/archives/volume7/number22/833-2018652796},
	doi = {10.5120/cae2018652796},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Flash ADCs employ multiple comparator circuits to introduce parallelism in data conversion. Having their speed limited only by transistor gate and comparator propagation delay, flash converters have the fastest signal conversion speeds amongst all ADC architecture implementations. This paper details the design of a low power 3-bit flash ADC with a 3V supply realised in 0.6 micron CMOS technology. The designed ADC exhibits a voltage resolution of 34.13 mV and draws 23.88 mW power at 2.17 MHz.

References

  1. N. Agrawal and R. Paily. An improved rom architecture for bubble error suppression in high speed flash adcs. In 2008 Annual IEEE Student Paper Conference, pages 1–5, Feb 2008.
  2. Mark Vesterbackar Erik Sail. A multiplexer based decoder for flash analog-to-digital converter. In IEEE region 10 TENCON conference, volume 4, pages 250–253, Nov 2004.
  3. Pradeep Kumar and Amit Kolhe. Design & implementation of low power 3-bit flash adc in 0.18 μm cmos. International Journal of Soft Computing and Engineering (IJSCE), 1(5):71–74, 2011.
  4. Swati Mishra, Abhay Vidyarthi, and Shyam Akashe. A novel folding technique for 3 bit flash adc in nanoscale. In Advanced Computing and Communication Technologies (ACCT), 2013 Third International Conference on, pages 307–311. IEEE, 2013.
  5. M. Rahman, K.L. Baishnab, and F.A. Talukdar. A novel rom architecture for reducing bubble and meta-stability errors in high speed flash adcs. In 20th International Conference on Electronics Communications and Computers, pages 15–19, 2010.
  6. P. V. Rahul, A. A. Kulkarni, S. Sankanur, and M. Raghavendra. Reduced comparators for low power flash adc using tsmc018. In 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), pages 1– 5, Aug 2017.
  7. B. Razavi. The flash adc [a circuit for all seasons]. IEEE Solid-State Circuits Magazine, 9(3):9–13, Summer 2017.
  8. Akashe Shyamm et al. Optimization of fat tree encoder for ultra high speed analog-to-digital converter using 45 nanometer technology. Optic-International Journal for Light and Electron Optics, 124(20):4490–4492, 2013.
  9. Timmy Sundstrom and Atila Alvandpour. A 2.5-gs/s 30- mw 4-bit flash adc in 90nm cmos. In NORCHIP, 2008., pages 264–267. IEEE, 2008.
  10. Rudy J Van de Plassche. CMOS integrated analog-todigital and digital-to-analog converters, volume 742. Springer Science & Business Media, 2013.
  11. Amana Yadav et al. Design and implementation of low power 3-bit flash adc using 180nm cmos technology. International Journal of Engineering Research and Applications, 6(6):77–82, 2016.

Keywords

Resistive ladder, Comparators, Bubble noise suppression, Hysteresis