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Reseach Article

DFM Challenges and Solutions for 14nm FinFET

by Ravi Dhanani, Bhavesh Soni
Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
Volume 2 - Number 3
Year of Publication: 2015
Authors: Ravi Dhanani, Bhavesh Soni

Ravi Dhanani, Bhavesh Soni . DFM Challenges and Solutions for 14nm FinFET. Communications on Applied Electronics. 2, 3 ( June 2015), 33-36. DOI=10.5120/cae-1693

@article{ 10.5120/cae-1693,
author = { Ravi Dhanani, Bhavesh Soni },
title = { DFM Challenges and Solutions for 14nm FinFET },
journal = { Communications on Applied Electronics },
issue_date = { June 2015 },
volume = { 2 },
number = { 3 },
month = { June },
year = { 2015 },
issn = { 2394-4714 },
pages = { 33-36 },
numpages = {9},
url = { },
doi = { 10.5120/cae-1693 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2023-09-04T19:40:38.043495+05:30
%A Ravi Dhanani
%A Bhavesh Soni
%T DFM Challenges and Solutions for 14nm FinFET
%J Communications on Applied Electronics
%@ 2394-4714
%V 2
%N 3
%P 33-36
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.

  1. Debajit Bhattacharya and Niraj K. Jha, "FinFETs: from Devices to Architectures", Vol 2014 , Article ID 365689, 21 pages, September 2014.
  2. Ruiqi Tian, Wong D. F, and Robert Boone, "Model based dummy placement for oxide chemical mechanical polishing manufacturability ", Design Automation Conference, pp 667-670, 2000.
  3. Ritesh Turukhia, Mark Ward, S. K Goel, Brady Benware, "Bridging DFM Analysis and Volume Diagnostics for Yield Learning – A case Study ", IEEE VLSI Test Symposium, pp 167-172, 2009.
  4. Ahmad Abdulghany, Rami Fathy, Luigi Capodieci, Piyush Pathak, Sriram Madhuvan, Shobhit Malik, "Smart Double-Cut Via Insertion Flow with Dynamic Design Rules Compliance for Fast New Technology Adoption", unpublished.
  5. Robert Boone, Domenico Loparco, Fabio Melchiori, Matt Thompson, "Critical Feature and Improvability Analysis: An Effective Path to DFM Closure", unpublished.
  6. Mentor Graphics Calire Design for Manufacturing related datasheets.
  7. KK Lin, Jeff Wilson, and Joe Kwan, "DFM Solutions for 14nm: Samsung and Mentor Graphics", On Demand Webinar, Decemeber 2014.
Index Terms

Computer Science
Information Sciences


Design for Manufacturability (DFM) Litho Friendly Design Critical Area Analysis Via Optimization Solution & SmartFill.