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Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

Neha Somra, Kanika Mishra, Ravinder Singh Sawhney. Published in Circuits and Systems.

Communications on Applied Electronics
Year of Publication: 2015
Publisher: Foundation of Computer Science (FCS), NY, USA
Authors: Neha Somra, Kanika Mishra, Ravinder Singh Sawhney

Neha Somra, Kanika Mishra and Ravinder Singh Sawhney. Article: Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width. Communications on Applied Electronics 2(7):1-5, August 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

	author = {Neha Somra and Kanika Mishra and Ravinder Singh Sawhney},
	title = {Article: Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width},
	journal = {Communications on Applied Electronics},
	year = {2015},
	volume = {2},
	number = {7},
	pages = {1-5},
	month = {August},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}


The FinFET transistor structure assures to rejuvenate the chip industry by rescuing it from the short-channel effects that limits the device scalability endured by current planar transistor structures. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and 5 nm oxide thickness. We report the drain saturation current is 0.0343453mA at Vg=1V and 0.0410523mA at Vg=1.5V which indicates approximately 20 percent hike in Id with increase in 0.5V gate voltage. We simulate the device for distinct fin thickness from 5 nm to 50 nm. In this thesis we report, for 32 nm gate length FinFET having above 21.33 nm fin width would consequence in short channel effects in spite of having high drain current.


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CMOS; silicon-on-Insulator (SOI); double-gate; Fin field-effect transistor (FinFET); tues gate; Drain Induced Barrier Lowering (DIBL).