Call for Paper

CAE solicits original research papers for the July 2023 Edition. Last date of manuscript submission is June 30, 2023.

Read More

FinFET Device Simulation and NAND Gate Implementation using DG FinFET

SocButtons v1.5

Kruti B. Modha, Bhavesh H. Soni. Published in Circuits and Systems.

FinFET Device Simulation and NAND Gate Implementation using DG FinFET
Communications on Applied Electronics
Year of Publication: 2016
Publisher: Foundation of Computer Science (FCS), NY, USA
Series: Volume 5 Number 5
Authors: Kruti B. Modha, Bhavesh H. Soni
10.5120/cae2016652304
Download full text

Kruti B Modha and Bhavesh H Soni. FinFET Device Simulation and NAND Gate Implementation using DG FinFET. Communications on Applied Electronics 5(5):33-35, July 2016. BibTeX

@article{10.5120/cae2016652304,
	author = {Kruti B. Modha and Bhavesh H. Soni},
	title = {FinFET Device Simulation and NAND Gate Implementation using DG FinFET},
	journal = {Communications on Applied Electronics},
	issue_date = {July 2016},
	volume = {5},
	number = {5},
	month = {Jul},
	year = {2016},
	issn = {2394-4714},
	pages = {33-35},
	numpages = {3},
	url = {http://www.caeaccess.org/archives/volume5/number5/621-2016652304},
	doi = {10.5120/cae2016652304},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In this paper it has been clarified that FinFET is a Fin Field effect transistor. It is promising substitute of CMOS in lower technology node. In this paper by making NAND Gate utilizing DG FinFET it is demonstrated that power utilization of IDDG FinFET is lesser than SDDG FinFET. At that point made an IDDG FinFET utilizing TCAD device and checked the impact of expanding the Fin width on the present qualities.

References

  1. M. Shrivastava, M. S. Baghini, A. B. Sachid, D. K. Sharma, and V.R. Rao, "A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET," IEEE Transactions on Electron Devices, vol. 55, no. 11, pp 3274-3282, November 2008.
  2. L. Mathew, Y. Du, A. V.-Y. Thean, M. Sadd, A. Vandooren, C. Prher, T. Steehehens, R. Mm. R. Rar, M. Zavala, D. Sing, S. Kafwl, J. Hughes, R. Shimer, S. Jaflepalfi, F. Wmmen, W. Zhangz, and Y. Nguyen, “CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET),” IEEE International SO1 Conference, April 2004.
  3. A. Muttreja, N. Agarwal, and N. K. Jha, "CMOS logic design with independent gate finfets," 25th international conference on computer design, pp 560-567, ICCD 2007.
  4. Ms. G. Devi Tejashwini, Mr. I.B.K. Raju, Mr. Gnaneshwara CharyPadmasri Dr. B.V. Raju, “Ultra-Low Power Circuit Design using Double-Gate FinFETs.”, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)
  5. Ankja Dubey and Sandeep Singh Gill, “Driving Capability of SG FinFET and IG FinFET”, 2015 IEEE
  6. Marc Swinnen and Ron Duncan,“Physical verification of finFET and FDSOI devices”, May 2, 2013
  7. Ravindra Singh Kushwah and Shyam Akashe, “FinFET Based Tunable Analog Circuit:Design and Analysis at 45 nm Technology”, Hindawi Publishing CorporationChinese Journal of Engineering Volume 2013

Keywords

Fin Field Effect Transistor(FinFET), Independently Driven Double Gate (IDDG), Simultaneously Driven Double Gate (SDDG)